• Journal of the Korea Society of Computer and Information
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• v.27 no.5
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• pp.11-19
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• 2022

In this paper, we propose a fault tolerant embedded system using memory redundancy on the full-virtualization based virtual machine monitor. The proposed virtual machine monitor first virtualizes main memory of embedded system utilizing efficient shadow page table scheme so that the embedded system runs as a virtual machine on the virtual machine monitor. The virtual machine monitor makes the backup of the embedded system run as another virtual machine by copying memory contents of the embedded system into memory space of backup system according to predefined schedules. When an error occurs in the target virtual machine, the corresponding standby virtual machine takes the role of target virtual machine and continues its operation. Performance evaluation studies show that such backups and switches of virtual machines are performed with minor performance degradation.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.1
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• pp.59-65
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• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.

• KIISE Transactions on Computing Practices
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• v.22 no.8
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• pp.363-368
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• 2016

A storage-based VDI (Virtual Desktop Infrastructure) system has the disadvantage of degraded performance when IOs for the VDI system are concentrated on the storage. The performance of the VDI system decreases rapidly especially, in case of the boot storm wherein all virtual desktops boot simultaneously. In this paper, we propose a main memory-based virtual desktop system managing virtual desktop images on main memory to solve the performance degradation problem including the boot storm. Performance of the main memory-based VDI system is improved by storing the virtual desktop image on the main memory. Also, the virtual desktop images with large size can be stored in the main memory using deduplication technology. Implementation of the proposed VDI system indicated that it has 4 times performance benefit than the storage-based VDI system in case of the boot storm.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.368-380
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• 2005

File systems for flash memory that is widely used as a storage device for mobile devices should provide not only high-performance data reads and writes but also a guarantee on the data integrity even on a power failure. In this paper, we explain the design and implementation of a file system for flash memory that considers flash memory's physical characteristics and the data layout in the file system to give an optimized write performance. This file system guarantees the reliability against various system failures including a power failure by using the transaction concept in write processing. In addition, the file system minimizes the memory usage by using a simple static mapping. In the paper, we also describe the implementation of the file system and compare its performance with other existing flash memory ille systems.

• Journal of the Korea Society of Computer and Information
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• v.25 no.4
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• pp.1-9
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• 2020

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5234-5251
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• 2018

It is well-known that virtualization technology can bring many benefits not only to users but also to service providers. From the view of system security and resource utility, higher resource sharing degree and higher system reliability can be obtained by the introduction of virtualization technology in distributed cloud. The small size time-sharing multiplexing technology which is based on virtual machine in distributed cloud platform can enhance the resource utilization effectively by server consolidation. In this paper, the concept of memory block and user satisfaction is redefined combined with user requirements. According to the unbalanced memory resource states and user preference requirements in multi-virtual machine environments, a model of proper memory resource allocation is proposed combined with memory block and user satisfaction, and at the same time a memory optimization allocation algorithm is proposed which is based on virtual memory block, makespan and user satisfaction under the premise of an orderly physical nodes states also. In the algorithm, a memory optimal problem can be transformed into a resource workload balance problem. All the virtual machine tasks are simulated in Cloudsim platform. And the experimental results show that the problem of virtual machine memory resource allocation can be solved flexibly and efficiently.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.305-311
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• 2005

Flash memory software running on cellular phones and PDAs need to be tested extensively to cope with abrupt power and media faults. For those tests, we designed and implemented a Flash memory emulator with fault injection features. The fault injection tester has provided a helpful framework for designing fault recovery schemes and also for analyzing fault damages to the FTL (Flash Translation Layer) and file system for a Flash memory based system. In this paper, we discuss Plash memory fault types and fault injection features implemented on this Flash memory emulator. We then discuss in detail a design flaw revealed during fault injection tests. Specifically, it was revealed that a scheme that was believed to improve reliability instead, turned out to be harmful. In addition, we discuss post-fault behaviors of the FTL and the file system.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• Journal of the Korea Society of Computer and Information
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• v.23 no.4
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• pp.81-88
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• 2018

In this paper, we present some problems with the Groupware Messenger functionality based on dot net 2.0 and implement a new design structure to solve them. They include memory leakage, slow processing, and client window memory crash. These problems resulted in the inconvenience of using instant messaging and the inefficient handling of office tasks. Therefore, in this paper, instant messaging functionality is implemented according to a new design architecture. The new system upgrades dot net 4.5 for clients and deploys the new features based on MQTT for the messenger server. We verify that the memory leak problem and client window memory crash issues have been eliminated on the system with the new messenger functionality. We measure the amount of time it takes to bind data to a set of messages and evaluate the performance, compared to a given system. Through this comparative evaluation, we can see that the new system is more reliable and performing.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.1-8
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• 2019

Modern computers provide tremendous computing capability and a large memory system. Hybrid memories consist of next generation memory devices and are adopted in high performance systems. However, the increased complexity of the microprocessor makes it difficult to operate the system effectively. In this paper, we propose a simple data migration method called Bandwidth-aware Data Migration (BDM) to efficiently use memory systems for high performance processors with hybrid memory. BDM monitors the status of applications running on the system using hardware performance monitoring tools and migrates the appropriate pages of selected applications to High Bandwidth Memory (HBM). BDM selects applications whose bandwidth usages are high and also evenly distributed among the threads. Experimental results show that BDM improves execution time by an average of 20% over baseline execution.