Browse > Article
http://dx.doi.org/10.14372/IEMEK.2022.17.1.59

Investigation on TLB Miss Impact through TLB Lockdown in Multi-core Systems  

Song, Daeyoung (Suresoft Tech Co., Ltd)
Park, Sihyeong (KETI)
Kim, Hyungshin (Chungnam National University)
Publication Information
IEMEK Journal of Embedded Systems and Applications / v.17, no.1, 2022 , pp. 59-65 More about this Journal
Abstract
Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.
Keywords
TLB miss; TLB lockdown; Memory profiling; Multi-core system;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388f/DDI0388F_cortex_a9_r2p2_trm.pdf/.
2 M. M. Papadopoulou, X. Tong, A. Seznec, A. Moshovos, "Prediction-based Superpage-friendly TLB Designs," Proc. of the 21st IEEE International Symposium on High Performance Computer Architecture, pp. 210-222, 2015.
3 Y. Li, R. Melhem, A. K. Jones, "PS-TLB: Leveraging Page Classification Information for Fast, Scalable and Efficient Translation for Future CMPs," ACM Transactions on Architecture and Code Optimization, Vol. 9, No. 4, 2013.
4 D. A. Patterson, J. L. Hennessy, "Computer Organization and Design: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)," 5th Ed., Morgan Kaufmann Publishers, 2013.
5 N. Amit, "Optimizing the TLB Shootdown Algorithm with Page Access Tracking," USENIX Annual Technical Conference (USENIX ATC 17), pp. 27-39, 2017.
6 C. Giuffrida, A. Kuijsten, A. S. Tanenbaum, "Enhanced Operating System Security Through Efficient and Fine-grained Address Space Randomization," Proc. of the 21st USENIX Security Symposium, pp. 475-490, 2012.
7 http://man7.org/linux/man-pages/man7/sched.7.html/
8 M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, R. B. Brown, "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," Proc. of the Fourth Annual IEEE International Workshop on Workload Characterization, pp. 3-14, 2001.
9 T. Ishikawa, T. Kato, S. Honda, H. Takada, "Investigation and Improvement on the Impact of TLB Misses in Real-time Systems," Proc. of OSPERT, 2013.
10 A. J. Pena and P. Balaji, "A Framework for Tracking Memory Accesses in Scientific Applications," Proc. of the 43rd International Conference on Parallel Processing Workshops, pp. 235-244, 2014.
11 S. A. Panchamukhi, F. Mueller, "Providing task Isolation Via TLB Coloring," Proc. of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 3-13, 2015.
12 G. Bernat, A. Colin, S. M. Petters, "WCET Analysis of Probabilistic Hard Real-time Systems," Proc. of the 23rd IEEE Real-Time Systems Symposium, pp. 279-288, 2002.
13 S. Chattopadhyay, Embedded System Design, 2nd Ed., PHI Learning Pvt. Ltd., 2013.
14 M. D. Bennett, N. C. Audsley, "Predictable and Efficient Virtual Addressing for Safety-critical Real-time Systems," Proc. of the 13th Euromicro Conference on Real-Time Systems, pp. 183-190, 2001.
15 https://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf/.
16 P. Parkinson, L. Kinnan, "Safety-critical Software Development for Integrated Modular Avionics," Suite," Proc. of the IEEE on pp. 3-14, 2001. Embedded System Engineering, Vol. 11, No. 7, pp. 40-41, 2003.
17 C. Mercer, R. Rajkumar, J. Zelenka, "Temporal Protection in Real-time Operating Systems," Proc. of the 11th IEEE Workshop on Real-Time Operating Systems and Software, pp. 79-83, 1994.
18 S. Mittal, "A Survey of Techniques for Architecting TLBs," Concurrency and Computation: Practice and Experience, Vol. 29, No. 10, 2017.
19 J. Y. Hwang, S. B. Suh, S. K. Heo, C. J. Park, J. M. Ryu, S. Y. Park, C. R. Kim, "Xen on ARM: System Virtualization Using Xen Hypervisor for ARM-based Secure Mobile Phones," Proc. of the 5th IEEE Consumer Communications and Networking Conference, pp. 257-261, 2008.
20 M. Masmano, I. Ripoll, P. Balbastre, A. Crespo, "A Constant-time Dynamic Storage Allocator for Real-time Systems," Real-Time Systems, Vol. 40, No. 2, pp. 149-179, 2008.   DOI
21 T. H. Romer, W.H. Ohlrich, A. R. Karllin, B. N. Bershad, "Reducing TLB and Memory Overhead Using Online Superpage Promotion," Proc. of the 22nd Annual International Symposium on Computer Architecture, pp. 176-187, 1995.