• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Sleep Medicine and Psychophysiology
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• v.4 no.1
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• pp.15-28
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• 1997

Longterm memory is encoded in the neuronal connectivities of the brain. The most successful models of human memory in their operations are models of distributed and self-organized associative memory, which are founded in the principle of simulaneous convergence in network formation. Memory is not perceived as the qualities inherent in physical objects or events, but as a set of relations previously established in a neural net by simultaneousy occuring experiences. When it is easy to find correlations with existing neural networks through analysis of network structures, memory is automatically encoded in cerebral cortex. However, in the emergence of informations which are complicated to classify and correlated with existing networks, and conflictual with other networks, those informations are sent to the subcortex including hippocampus. Memory is stored in the form of templates distributed across several different cortical regions. The hippocampus provides detailed maps for the conjoint binding and calling up of widely distributed informations. Knowledge about the distribution of correlated networks can transform the existing networks into new one. Then, hippocampus consolidats new formed network. Amygdala may enable the emotions to influence the information processing and memory as well as providing the visceral informations to them. Cortico-striatal-pallido-thalamo-cortical loop also play an important role in memory function with analysis of language and concept. In case of difficulty in processing in spite of parallel process of informations, frontal lobe organizes theses complicated informations of network analysis through temporal processing. With understanding of brain mechanism of memory and information processing, the brain mechanism of mental phenomena including psychopathology can be better explained in terms of neurobiology and meuropsychology.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.10 s.181
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• pp.2461-2468
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• 2000

In this paper, single fiber pull-out test is used to measure the interfacial bonding shear strength of $Ti_{50}-Ni_{50}$ shape memory alloy composite with temperature. Fiber and matrix of $Ti_{50}-Ni_{50}$ shape memory alloy composite are respectively $Ti_{50}-Ni_{50}$ shape memory alloy and epoxy resin. To strengthen the interfacial bonding shear stress, various surface treatments are used. They are the hand-sanded surface treatment, the acid etched surface treatment and the silane coupled surface treatment etc.. The interfacial bonding shear strength of surface treated shape memory alloy fiber is greater than that of surface untreated shape memory alloy fiber by from 10% to 16%. It is assured that the hand-sanded surface treatment and the acid etched surface treatment are the best way to strengthen the interfacial bonding shear strength of $Ti_{50}-Ni_{50}$ shape memory composite. The best treatment condition of surface is 10% HNO$_3$ solution in the etching method to strengthen the interfacial bonding shear strength of $Ti_{50}-Ni_{50}$ shape memory alloy composite.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.61-70
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• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• KIISE Transactions on Computing Practices
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• v.22 no.10
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• pp.497-503
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• 2016

Emerging next-generation storage technologies such as non-volatile memory will help eliminate almost all of the storage latency that has plagued previous storage devices. In conventional storage systems, the latency of slow storage devices dominates access latency; hence, software efficiency is not critical. With low-latency storage, software costs can quickly dominate memory latency. Hence, researchers have proposed the memory mapped file I/O to avoid the software overhead. Mapping a file into the user memory space enables users to access the file directly. Therefore, it is possible to avoid the complicated I/O stack. This minimizes the number of user/kernel mode switchings. In addition, there is no data copy between kernel and user areas. Despite of the benefits in the memory mapped file I/O, its overhead still needs to be addressed, as the existing mechanism for the memory mapped file I/O is designed for slow block devices. In this paper, we identify the overheads of the memory mapped file I/O via experiments.

• The Korean Journal of Archival Studies
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• no.67
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• pp.267-318
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• 2021

The purpose of this study is to analyze how the "memory approach" has affected archival methodology and activities, and suggest the directions of archival activities in each field. Although there have been many discussions on the memories and collective memories in Archival Studies, it is necessary to analyze them more practically from the viewpoint of archival activism. In this study, the memory approaches in archival discourse are classified into four categories in terms of archival activism; i) the role of archives as social memory organizations, ii) the memory struggle for finding out the truth of the past, iii) archival activities of restorative justice for people who suffer from trauma memories after social disasters and human rights violations, and iv) the memory process of communities' archiving for strengthening community identities. The meaning and issues are analyzed for each category, and the practice based on archival expertise and political and social practices are examined together as necessary competencies for archival activism.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.539-548
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• 2015

In this paper, shared memory feature was developed in multi-core system with different OS for different processor-specific bus, while conducting an experiment on shared memory feature between the two processors based on embedded Linux system. For the purpose of developing shared memory in dual bus structure, memory controller was used, while managing shared memory segment through list data structure. For AMP multi-core test, Linux OS was installed in 2 processor cores. In addition, it verified the creation and use of shared memory by using kernel module implemented to test shared memory.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Journal of Computing Science and Engineering
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• v.8 no.3
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• pp.157-172
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• 2014

Contemporary embedded systems often use NAND flash memory instead of hard disks as their swap space of virtual memory. Since the read/write characteristics of NAND flash memory are very different from those of hard disks, an efficient page replacement algorithm is needed for this environment. Our analysis shows that temporal locality is dominant in virtual memory references but that is not the case for write references, when the read and write references are monitored separately. Based on this observation, we present a new page replacement algorithm that uses different strategies for read and write operations in predicting the re-reference likelihood of pages. For read operations, only temporal locality is used; but for write operations, both write frequency and temporal locality are used. The algorithm logically partitions the memory space into read and write areas to keep track of their reference patterns precisely, and then dynamically adjusts their size based on their reference patterns and I/O costs. Without requiring any external parameter to tune, the proposed algorithm outperforms CLOCK, CAR, and CFLRU by 20%-66%. It also supports optimized implementations for virtual memory systems.