• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.620-621
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• 2008

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide-based thin-film transistors (TFTs) on glass and plastic substrates although in general high voltage operating devices have been mainly studied considering transparent display drivers. However, low voltage operating oxide TFTs with transparent electrodes are very necessary if we are aiming at logic circuit applications, for which transparent complementary or one-type channel inverters are required. The most effective and low power consuming inverter should be a form of complementary p-channel and n-channel transistors but real application of those complementary TFT inverters also requires electrical- and even photo-stabilities. Since p-type oxide TFTs have not been developed yet, we previously adopted organic pentacene TFTs for the p-channel while ZnO TFTs were chosen for n-channel on sputter-deposited $AlO_x$ film. As a result, decent inverting behavior was achieved but some electrical gate instability was unavoidable at the ZnO/$AlO_x$ channel interface. Here, considering such gate instability issues we have designed a unique transparent complementary TFT (CTFTs) inverter structure with top n-ZnO channel and bottom p-pentacene channel based on 12 nm-thin nano-oxide/self assembled monolayer laminated dielectric, which has a large dielectric strength comparable to that of thin film amorphous $Al_2O_3$. Our transparent CTFT inverter well operate under 3 V, demonstrating a maximum voltage gain of ~20, good electrical and even photoelectric stabilities. The device transmittance was over 60 % and this type of transparent inverter has never been reported, to the best of our limited knowledge.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.179-184
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• 2016

The electrical load testing system developed from this study was designed to control rated-capacity-testing or variable-load-testing in an active and precise manner and save electric energy during testing, and also to convert the saved electric energy through the electrical load testing system to grid line. As for the device under testing, it was designed to be applied to not only transformer, rectifier, voltage regulator, inverter which require grid voltage source but, also applied to electric power, aerogenerator, photovoltaic, hybrid generator, battery, etc. which do not require grid voltage source. The system was designed to return the power consumed during the testing to the grid line by connecting the synchronizing pwm inverter circuit to the grid voltage source, and was also made to enable the being-tested system from disuse of approximately 93.4% energy when compared to the conventional load testing system which has used the passive resistor.

• Composites Research
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• v.24 no.1
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• pp.37-44
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• 2011

In this paper, Particle Swarm Optimization(PSO) is applied to the design of the Frequency Selective Surface(FSS) and residual stresses of hybrid radome is predicted. An equivalent circuit model with Square Loops arrays was derived and then PSO was applied for acquiring the optimized geometrical parameters with proper resonant frequency. Residual stresses occur in the FSS embedded composite structures after cocuring and have a great influence on the strength of the FSS embedded composite structures. They also effect transmission quality because of delamination. Therefore, the thermal residual stresses of FSS embedded composite structures were analyzed using finite element analysis with considering the effects of FSS pattern, and composite stacking sequence.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.115-124
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• 2004

In this paper, we introduce the advanced compact transmission line with periodic stepped stubs. They are more effective than normal stubs in ATL. The short stepped stubs loading of transmission line work as effective shunt capacitance and that was proved by equivalent circuit based on transmission line theory and quasi-static analysis. And the compact branch-line coupler and the compact rat-race coupler via proposed compact microstrip line were designed at 1.8 ㎓. They have 677 ㎟ and 913 ㎟, respectively, and they are 62% and 45% of normal design.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.685-694
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• 2015

In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of $64{\times}64$, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of $128{\times}128$, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Journal of Sensor Science and Technology
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• v.5 no.1
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• pp.43-50
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• 1996

This paper presents a manufacture of the multiple subjects biotelemetry system using custom CMOS IC fabricated $1.5{\mu}m$ n-well process technology. The implantable circuits of the system except sensor interface circuits including FM transmitter are fabricated on a single chip with the sire of $4{\times}4mm^{2}$. It is possible to assemble the implantable system in a hybrid package as small as $3{\times}3{\times}2.5cm$ by using this chip, It's main function is to enable continuous measurement simultaneously up to 7-channel physiological signals from the selected one among 8 subjects. Another features of this system are to enable continuous measurement of physiological signals, and to accomplish ON/OFF switching of an implanted battery by subject selection signal with command signal from the external circuit. If this system is coupled with another appropriate sensors in medical field, various physiological parameters such as pressure, pH and temperature are to be measured effectively in the near future.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.809-815
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• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.4
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• pp.440-446
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• 2011

In this paper, a X-band 50 W pulsed solid state power amplifier(SSPA) is designed and fabricated for radar systems. The SSPA consists of a driver amplifier, a high power amplifier, and a pulse modulator. The high power stage employes four 25 W GaAs FET to deliver 50 W at X-band. To meet the stringent target specification for the SSPA, we used a new hybrid pulse switching method, which combine the advantage of pulse modulation and bias switching method. The fabricated SSPA shows a power gain of 44.2 dB, an output power of 50 W over a 1.12 GHz bandwidth. Also, pulse droop < 1 dB meet the design goals and a rise/fall time is less than 12.45 ns. Fabricated X-band pulsed SSPA size is compact with overall size of $150{\times}105{\times}30\;mm^3$.