• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.38-42
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• 2005

CMOS analog lowpass filters using speech signal bandwidth for a Asymmetrical Digital Subscriver Line(ADSL) modem are presented. Designed active lowpass filters are composed of the CMOS complementary high-swing cascode stage which can increase transconductance of an active element. As a result, their cutoff frequency are 138kHz and 1,100kHz respectively. A low-voltage high-swing cascode integrator which improved on a gain and unit gain frequency used to design the filters. The designed filters are verified by HSPICE simulation with the $0.251{\mu}m\;CMOS\;n-well$ Parameter and a single 2.5V power supply.

• Journal of Information Display
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• v.3 no.2
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• pp.1-5
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• 2002

A CMOS driving circuit for active matrix type polymer electroluminescent displays was designed to develop an on-chip microdisplay on the single crystal silicon wafer substrate. The driving circuit is a conventional structure that is composed of the row, column and pixel driving parts. 256 gray scales were implemented using pulse amplitude modulation method. The 2-transistor driving scheme was adopted for the pixel driving part. The layout was carried out considering the compatibility with the standard CMOS process. Judging from the layout of the driving circuit, it turns that it is possible to implement a high-resolution display about 400 ppi resolution. Through the HSPICE simulation, it was verified that this circuit is capable of driving a VGA signal mode display and implementing 256 gray levels.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1535-1538
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• 2002

The flexibility of content addressable mem-ory (CAM) can greatly be extended through the use of trits (ternary digits) Trits consist of binary logical values “0” and “1” with addition of “x” (“dont’t care”). The “dont’t care“is extremely useful for providing com- pact representation of sets of bit strings. In this paper, we propose a new ternary CAM with Hamming distance search functions. Each memory cell in the CAM consists of a pair of lambda diodes which can store trits, namely, a logical “0”, “1” and “x” (“dont’t care“). The CAM can compare stored data and an input data in parallel, and find stored data with Hamming distance within a certain range (“near match“). Also, the interrogation characteristics of the ternary CAM are analyzed in detail. Furthermore, the results obtained these analyses are fully confirmed by simulation using the circuit analysis program HSPICE.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.95-96
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• 2008

A new voltage-driven pixel circuit using soluble-processed organic thin film transistors (OTFTs) for an active matrix organic light emitting diode (AMOLED) is proposed. The proposed circuit is composed of four switching TFTs, one driving TFT and one storage capacitor. The proposed circuit can compensate for the degradation of OLED current caused by the threshold voltage shift of the OTFT. The simulation results show that the variation of OLED current corresponding to a 3V threshold voltage shift is decreased by 30% compared to the conventional 2TlC structure.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3181-3183
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• 2000

As the fact that the simple data of text and sound in early year have been changed to be high quality images and sounds. PLL(Phase-Locked Loop) system plays an important role in communication system. VCO(Voltage Controlled Oscillator) is the most important part in PLL system because it can have critical effects on operation of PLL. Recently, it has been raised the necessity of high speed and high accuracy circuit application. In this paper, a new differential voltage clamped VCO using negative-skewed path is suggested. Using a dual-delay scheme to implement the VCO, higher operation frequency and wider tuning are achieved simultaneously. The dual-delay scheme means that both the negative skewed delay paths and the normal delay paths exist in the same ring oscillator. The negative skewed delay paths decrease the unit delay time of the ring oscillator below the single inverter delay time. As a result, higher operation frequency can be obtained. The whole characteristics of VCO are simulated by using HSPICE. Simulation results show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.

• ETRI Journal
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• v.37 no.3
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• pp.584-594
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• 2015

To date, many different kinds of logic styles for hardware countermeasures have been developed; for example, SABL, TDPL, and DyCML. Current mode-based logic styles are useful as they consume less power compared to voltage mode-based logic styles such as SABL and TDPL. Although we developed TPDyCML in 2012 and presented it at the WISA 2012 conference, we have further optimized it in this paper using a binary decision diagram algorithm and confirmed its properties through a practical implementation of the AES S-box. In this paper, we will explain the outcome of HSPICE simulations, which included correlation power attacks, on AES S-boxes configured using a compact NMOS tree constructed from either SABL, CMOS, TDPL, DyCML, or TPDyCML. In addition, to compare the performance of each logic style in greater detail, we will carry out a mutual information analysis (MIA). Our results confirm that our logic style has good properties as a hardware countermeasure and 15% less information leakage than those secure logic styles used in our MIA.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.341-342
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• 2007

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2081-2086
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• 2015

The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.