• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.4
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• pp.343-350
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• 2014

Divisive hierarchical clustering algorithms iterate the process of decomposition and clustering data recursively. In each recursive call, data in each cluster are arbitrarily selected and thus, the total clustering time can be increased, which causes a problem that it is difficult to apply the process of clustering neighbor vehicular position data in vehicular localization. In this paper, we propose a new heuristic algorithm for speeding up the clustering time by eliminating randomness of the selected data in the process of generating the initial divisive clusters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12B
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• pp.1103-1111
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• 2008

Internet routers forward an incoming packet to an output port toward its final destination through IP address lookup. Since each incoming packet should be forwarded in wire-speed, it is essential to provide the high-speed search performance. In this paper, IP address lookup algorithms using binary search are studied. Most of the binary search algorithms do not provide a balanced search, and hence the required number of memory access is excessive so that the search performance is poor. On the other hand, binary-search-on-range algorithm provides high-speed search performance, but it requires a large amount of memory. This paper shows an optimized binary-search-on-range structure which reduces the memory requirement by deleting unnecessary entries and an entry field. By this optimization, it is shown that the binary-search-on-range can be performed in a routing table with a similar or lesser number of entries than the number of prefixes. Using real backbone routing data, the optimized structure is compared with the original binary-search-on-range algorithm in terms of search performance. The performance comparison with various binary search algorithms is also provided.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.485-497
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• 2009

In this paper, we described DVB-S2 system for mobility. cross layer coding technique are needed to maintain the performance in deep fading channel. Cross layer coding is divided into two kinds of level. First level is Physical layer coding and, second layer is link layer or upper layer coding. Fixed on DVB-S2 short frame coding method as a physical layer, we simulated the various coding method as an upper layer coding. Furthermore, we analyzed the performance of each coding method on according to mobile vehicle speed, data rate, interleaving memory size, and IP packet size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.663-668
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• 2003

With the advent of high speed networking technology, computers connected to the high-speed networks tend to consume more of their CPU cycles to process data. So one of the solutions to improve the performance of the computers is to reduce the CPU cycles for processing the data. As the consumption of the CPU cycles is increased in proportion to the number of the packets per second to be processed, reducing the number of the packets per second by increasing the length of the packet is one of the solutions. In order to meet this requirement, two types of jumbo packets such as jumbograms and jumbo frames have already been standardized or being discussed. In case that the jumbograms and general packets are interleaved and scheduled together in a router, the jumbogrms may deteriorate the QoS of the general packets due to the transfer delay. They also frequently exhaust the memory with storing the huge length of the packets. This produces the congestion state easily in the router that results in the loss of the packets. In this paper, we analyze the problems in processing the jumbo packets and suggest a noble solution to overcome the problems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.900-907
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• 2009

With the introduction of the concept such as QoS, QoE, and MOS for the multimedia services over the high-speed network the user's concern about the degradation in the perceived quality of service for the conventional data service has become a new problem to the Internet service providers. In this work we propose a method to evaluate the subjective QoE such as MOS for the high-speed Internet service, where the round trip time for the data transfer is taken into account as a performance parameter for the experienced delay. We develop a tool to evaluate an MOS that enables us to investigate the behavior of users for diverse delay times for the web access service, via which we analyze the sensitivity of users with regard to MOS as a function of delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11B
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• pp.772-783
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• 2005

In this paper, we propose an effective multicasting protocol in wireless ad-hoc networks. Conventional wired and wireless network multicast protocols do not perform well in wireless ad hoc networks because they were designed without consideration of ad hoc environments such as node mobility, limited bandwidth, high error probability. To solve this problem, some multicasting protocols for ad hoc network have been proposed in the literature. However, these protocols can not provide high packet delivery ratio, low control packet overhead and low expended bandwidth at the same time. Therefore, in this paper, we propose RTMA that improves multicasting performance in wireless ad hoc networks. RTMA calculates its current region from its position information by using GPS in order to make tree among the multicast group nodes in the same region. The proposed region-based tree method is for high packet delivery ratio, low control packet overhead when many senders send data packets. RTMA makes a reliable tree by using speed information to fill a gap of the weak points of the tree structure. When searching the routing path, RTMA selects the reliable path excluding high speed nodes.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.5
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• pp.243-247
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• 2009

For obtaining high speed data rate, underwater acoustic communication has several problems by the different environmental problem compared to wireless communication. To overcome this problem, the research is going steadily. In this paper, the property of underwater acoustic channel is considered, and the explanation of recently various method of transmitting and receiving and the domestic and foreign trend of underwater acoustic communication are taken into account.