• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.217-218
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• 2006

This paper presents an investigation on the characteristics for new micro tool dynamometer by using the ultrahigh-speed air turbine spindle. Recently, the ultrahigh-speed micro flat endmilling has been investigated actively due to request of accuracy improvement and productivity of die and mould manufacturing. To perform efficient ultrahigh-speed micro flat endmilling, evaluation of ultrahigh-speed machinability must be studied preferentially and it can be identified by investigation of cutting force. The cutting forces in ultrahigh-speed micro flat endmilling can be measured by micro tool dynamometer. But general dynamometer has low natural frequency and so is improper for measuring very high frequency cutting forces in ultrahigh-speed micro flat endmilling. In this study, the micro tool dynamometer which has very high natural frequency is newly designed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.38-49
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• 1998

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed for real-time or high-speed(faster than real-time) simulators. This paper presents an enhanced strategy in which high computing power can be provided by parallel processing of DSP processors with communication links. DSP system is designed for general purpose. Parallel DSP system can be easily expanded by just connecting new DSP modules to the system. General urpose DSP modules and a VME interface module was developed. New model and techniques for the task allocation are also presented which take into account the special characteristics of parallel I/O and computation. As a realistic cost function of task allocation, we suggested 'simulation period' which represents the period of simulation output intervals. Based on the development of parallel DSP system and realistic task allocation techniques, we cound achieve good efficiency of parallel processing and faster simulation speed than real-time.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1020-1022
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• 1993

The speed control associated with do send motors for direct-drive applications of mobile robot is considered. In odor to the high-performance operation of dc servo motor, drive circuits is controlled Pulse Width Modulations. In this case, PWM driving circuit has nonliner charactristics. This circuit composed of H-type bridge with freewheeling diodes in odor to deal with storage energy of motor's inductance and also control method is developed. At resultes, speed charactristics of motor is shown lineristics. In oder to speed control of motor. The opertion of phase-locked servo system is described and a linear discrete model is developed to their behavior. Thise model discussed are the design problems, speed variation.

• Nuclear Engineering and Technology
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• v.53 no.7
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• pp.2289-2294
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• 2021

In the present study, an original spark plasma sintering-reactive synthesis (SPS-RS) method for minerallike ceramic materials based on SrAl₂Si₂O₈ feldspar-like skeleton structure was used for the first time, promising solid-state matrices for reliable immobilization of high-energy ⁹⁰Sr. The method is based on the "in-situ" reaction of a mixture of SrO, Al₂O₃ and SiO₂ oxides when heated by a unipolar pulsed current under compacting pressure. The phase and elemental composition structure were studied. The dynamics of the consolidation of the reaction mixture of oxides was studied in the range of 900-1200 ℃. The study found the temperature of the high-speed (minutes) SPS-RS formation of single-phase SrAl₂Si₂O₈ composition ceramic in the absence of intermediate reaction products with a relative density of up to 99.2% and compressive strength up to 145 MPa and a strontium leaching rate of 10^-4g/cm²·day.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.408-409
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• 2009

The memory characteristics of charge trap memory capacitor with high-k materials were investigated. I-V characteristics of the fabricated device with band gap engineered tunneling gate stacks consisted of $SiO_2$, $ZrO_2$, $Al_2O_3$ dielectrics were evaluated and compared with the one consisted of $SiO_2$ tunneling dielectric. The memory capacitor including engineered tunneling dielectrics of ($Al_2O_3/ZrO_2/SiO_2$) shows the fastest PIE speed and long data retention time.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

• Journal of IKEEE
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• v.23 no.3
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• pp.1038-1045
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• 2019

This paper describes high-speed duobinary transceiver design techniques which are widely used to increase data-rate despite limited channel bandwidth. At high data-rate, signal level is severely degraded as signal frequency becomes larger than the channel bandwidth. Mathematically, a duobinary signal has lower frequency components compared to a Non-Return-to-Zero signal for the same data-rate. Therefore, by using the duobinary signaling, the signal loss can be effectively reduced in physical channel environment as compared to the Non-Return-to-Zero signaling. The mathematical basis of duobinary signaling, and its applications to high-speed transceiver design are investigated in this paper.

• KIEE International Transactions on Electrophysics and Applications
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• v.2C no.5
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• pp.258-261
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• 2002

Electrical forming dependent current-voltage (I-V) and numerically derived differential conductance(dI／dV) characteristics have been presented in the multi-layer nano-crystalline silicon／oxygen (no-Si／O) superlattice. Distinct staircase-like features, indicating the presence of resonant tunnel barriers, are clearly observed in the dc I-V characteristics. Also, all samples showed a continuous change in current and zero conductivity around OV corresponding to the Coulomb blockade in the calculated dI／dV-V curve. Also, Ra-man scattering measurement showed the presence of a nano-crystalline Si structure. This result becomes a step in the right direction for the fabrication of silicon-based optoelectronic and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in high speed and low power silicon MOSFET devices of the future.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.14-18
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• 1995

Although structural ceramics have excellent mectanical properties, it is very difficult to grind with high efficiency and high quality because of their high strength, hardness, and brittleness. Unfortunately machined ceramics often contain surface damages such as micro fracture and crack on account of brittle fracture. Therefore, is is important to minimize the brittle fracture. The present paper examines grinding characteristics of representative structural ceramics,such as Al /sab 2/O /sab 3/, SiC, Si /sab 3/ N /sab 4/. Effects of grinding variables including table speed and depth of cut on the grinding performance were investigated. Experimental results show that the surface quality is related to the specific grindings energy. The higher specific energy results in the better surface quality.