• Transactions of the Korean Society of Mechanical Engineers A
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• 제28권7호
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• pp.1029-1037
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• 2004

High-speed/precision servomechanisms have been widely used in the manufacturing and semiconductor industries. In order to ensure the required high-speed and high-precision specifications in servomechanisms, an integrated design methodology is required, where the interactions between mechanical and electrical subsystems will have to be considered simultaneously. For the first step of the integrated design process, it is necessary to obtain not only strict mathematical models of separate subsystems but also formulation of an integrated design problem. A two-degree-of-freedom controller described in the discrete-time domain is considered as an electrical subsystem in this paper. An accurate identification process of the mechanical subsystem is conducted to verify the obtained mathematical model. Mechanical and electrical constraints render the integrated design problem accurate. Analysis of the system performance according to design and operating parameters is conducted for better understanding of the dynamic behavior and interactions of the servomechanism. Experiments are performed to verify the validity of the integrated design problem in the x-Y positioning system.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.995-997
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• 2009

$In_2O_3$ thin-film transistors (TFTs) were fabricated on various dielectrics [$SiO_2$ and self-assembled nanodielectrics (SANDs)] by spin-coating a $In_2O_3$ film precursor solution consisting of methoxyethanol (solvent), ethanolamine (EAA, base), and $InCl_3$ as the $In^{3+}$ source. Importantly, an optimized film microstructure characterized by the high-mobility $In_2O_3$ 004 phase, is obtained only within a well-defined base: $In^{3+}$ molar ratio. The greatest electron mobilities of ~ 44 $cm^2$, for EAA:$In^{3+}$ molar ratio = 10, $V^{-1}s^{-1}$, is measured for $n^+$-Si/SAND/$In_2O_3$/Au devices. This result combined with the high $I_{on}:I_{off}$ ratios of ~ $10^6$ and very low operating voltages (< 5 V) is encouraging for high-speed applications.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.28-32
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• 1997

This study aims at developing the high speed/intelligent machining system suing the plug/play method of an open architecture controller. The plug/play technology by the Application Specific Function (ASF), can readily implement the open architecture controller into various machining system or other automatic equipments. For the open architecture controller, this study developed the open HMI, screen editor, ASF, visual builder, and controller OS technology as software components. On the other hand, we developed the I/O module and main board as control hardware system. This study, as an example, presents integration of individual component technologies for the plug/play type open architecture CNC system.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• 제3권2호
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• pp.18-25
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• 2004

As using of network Increases rapidly, performance of system has been deteriorating because of the overhead and bottleneck. Nowadays, high speed I/O network standard, that is a sort of InfiniBand, PCI Express and so on, has come out to improve the limites of traditional I/O bus. The InfiniBand provides some protocols to service the applications such as SDP, SRP and IPoIB. In our paper, We explain the architecture of SDP(Socket Direct Protocol) and its features in channel based I/O network. And so, we provide a result of performance evaluation of SDP which is compared with current network protocol. Our experimental results also show that SDP is better than TCP/IP protocol.

• Journal of the Institute of Electronics Engineers of Korea SC
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• 제44권1호
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 한국공작기계학회 2004년도 춘계학술대회 논문집
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• pp.359-364
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• 2004

A high-speed and intelligent CNC system has been developed by Turbotek Co., Ltd. This paper presents the study for commercialization of the developed CNC system. In order to acquire stability and reliability of the developed CNC system, its hardwares and softwares ate improved. The CNC main unit is revised to a compact box-type CNC controller. Moreover, the integrated CNC main unit that has built-in and expandable I/O modules is also developed. Remote monitoring, fault diagnosis End NURBS interpolation functions are realized on the CNC system as software modules. Through these efforts, the developed CNC system can be loaded on machine tools successfully.

• Proceedings of the KIEE Conference
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.212-214
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• 2005

The MDDI(Mobile Digital Display Interface) standard is an optimized high-speed serial interconnection technology developed by Qualcomm and supports the VESA(Video Electronics Standard Association). It increases reliability and reduces power consumption in clamshell phones by decreasing the number of wires to interconnect with the LCD display. In this paper, the MDDI host is designed using VHDL and implemented on FPGA. We demonstrates that the MDDI host is connected with S3CA460 LCD controller is designed by Samsung Electronics Co. and display a steal image to the LCD.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.75-80
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• 1992

This paper deals with the design scheme of the custom control circuit for optimizing the interface of peripheral devices to general-purpose controllers for the high speed digital system. When the various peripheral devices such as memory, I/O devices and buffers which operate at low speed are interfaced to the microprocessor which operates at high speed, inserting the proper wait state to the processor is required. The proposed scheme designed with random logic may be applied to the high performance graphic system like the X-terminal. This circuit provides the flexibility and system independancy for the optimum digital system design.