• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of Welding and Joining
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• v.8 no.1
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• pp.62-69
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• 1990

Being focused on the recent studies that the fatigue strength of resistance spot weldmentes can be improved by using ellipsoidal weld nuggets, the voltage and temperature distribution in resistance spot weldments were simulated for the various rectangular electrodes which had the different aspect ratio of the contact area. Because the electrode shape was not axi-symmetric, the solution domain for simulation should be three dimensional. A series of experiments were carred out to verify the analytically obtained temperature distribution in the weldment. From the calculational and experimental results, it could be revealed that the nugget took the form of ellipsoid, while both results showed a considerable discrepancy for the high aspect ratio.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.29.1-29.1
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• 2010

ZnO 는 톡특한 물리적 화학적 성질을 가지고 있는 반도성 물질이기 때문에 최근 광전자 소자인 LED, TFT, 광센서 등에 적용하려는 연구가 많은 관심을 받고 있다. 특히 1차원 ZnO 나노구조는 박막보다 높은 결정성과 물리, 화학적으로 안정하고 표면적이 매우 넓어 많은 연구가 진행되고 있지만, 대량으로 간단하며 저렴하게 생산하기 위해서 친환경적이며 적은 시간으로 합성을 해야 한다. 그래서 최근 수열 합성법을 이용하여 합성이 많이 이루어지고 있지만, ZnO 나노막대 제조 중 기존에 보고된 방법은 대부분 aspect ratio가 낮으며, 저가의 용액 기반으로 높은 aspect ratio를 가지는 나노 선을 제작하기 어려운 실정이다. 또한 용액기반의 성장에서는 기판과의 격자 상수와 열팽창 계수의 차이로 인해 기판과의 adhesion 이 매우 낮아 adhesion layer를 증착 하여 나노 막대을 제작하는 것이 발표가 되고 있다. 하지만 또 하나의 공정이 더해지기 때문에 복잡해지고, 소자에 응용하기에는 한계점이 보인다. 그렇기 때문에 이번 연구에서는 성장 시 Zn 소스가 소모가 다 되었을 시 성장 용액을 교체하는 과정에서 성장 온도와 같이 유지 시킨 뒤에 성장을 하는 방법으로 수직 방향으로 10 um 의 길이를 가지는 ZnO 나노막대의 합성을 가능하게 하였다.

• Journal of Magnetics
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• v.10 no.2
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• pp.58-62
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• 2005

Periodic magnetic nanodot arrays were successfully produced on glass substrates by interference laser lithography and electron beam lithography methods. Magnetic force microscopy (MFM) observation was carried out on fabricated nanodot arrays. MFM tip induced magnetization effects were clearly observed in ferromagnetic elliptical nanodots varying in material and aspect ratio. Fe-Cr dots with a high aspect ratio show reversible switching of the single domain magnetization state. At the same time, Co nanomagnets with a low aspect ratio exhibit tip induced transitions between the single domain and the vortex state of magnetization. The simple nanolithography is potentially an efficient method for fabrication of patterned magnetic arrays.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1064-1067
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• 2001

Micro drilling is used in the production of fuel injection nozzle, watch, camera, air bearing and pinted circuit boards(PCB) are demanded for high precision. Recently industries of precision production require more small hole, high aspect ratio and high speed working for micro deep hole drilling. But the undesirable characteristics of micro drilling is the small signal to noise ratios, wandering motion of drill, high aspect ratio and the increase of cutting force as cutting depth increase. So in this paper to obtain the optimization of cutting condition a study on the characteristics of micro deep hole drilling used Tool dynamometer is proposed.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1974-1976
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• 1996

An electrostatically driven comb actuator with $525{\mu}m$ height was fabricated using (110) Si anisotropic etching in the Potassium Hydroxide(KOH) solution. The etch-rate and etch-rate ratio are strongly dependent on the weight % and temperature of KOH solution. We developed the optimal condition for the anisotropic etching on (110) wafer with varying these conditions. The force that the comb-drive actuator generates is inversely proportional to the distance of gap and proportional to the height of the comb electrodes. The electrodes must have the high aspect ratio. The (110) Si anisotropic etching is very useful to get a high aspect ratio structure.

• Journal of Korean Vacuum Science & Technology
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• v.6 no.2
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• pp.79-83
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• 2002

As Ag does not form my silicide on Si surfaces, Ag wire is a candidate for self-assembled nanowire on the reconstructed and single-domain Si(5 5 12)-2 $\times$ 1. In the present study, various Ag coverages and post-annealing temperatures had been tested to fabricate a Ag nanowire with high aspect ratio. When Ag coverage was less than 0.03 ML and the post-annealing temperature was 500(C, Ag atoms preferentially adsorbed on the tetramer sites resulting in Ag wires with an inter-row spacing of ~5 nm. However, its aspect ratio is relatively small and its height is also not even. On the other hand, the Ag-posited surface completely loses its reconstruction even with the same annealing at 500 $\^{C}$ if the initial coverage exceeds 0.05 ML. But the additional subsequent annealing at 700$\^{C}$ and slow-cooling process recovers the well-ordered Ag chain with relatively high aspect ratio on the same tetramer sites. It can be understood that, in the double step annealing process, the lower temperature annealing is required for cohesion of adsorbed Ag atoms and the higher temperature annealing is for providing Ag atoms to the tetramer sites.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.601-604
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• 2010

In this study, the piezoelectric energy harvester was investigated employing the pillar structure with the diameter size of 50~500 um. Usually, the aspect ratio between the height and diameter was related with the piezoelectric performance. High aspect ratio was showed the low electric noise and high piezoelectric properties than low aspect ratio. Therefore, we have selected the Su-8 photo-resist and modified lithography process to manufacture the pillar structure with height above the 250 ${\mu}m$. In this presentation, we will report the process and properties of micro pillar structure based on the PMN-PZT (Pb$(Mg_{1/3}Nb_{2/3})O_3$-PbZrTiO$_3$) materials.

• Current Photovoltaic Research
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• v.5 no.1
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• pp.9-14
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• 2017

The screen printing technique is one of process to form electrode for crystalline silicon solar cell and has been studied a lot, because it has many advantages such as low price, high efficiency and mass production due to simple and fast process. The reason why electrode formation is important is for influence of series resistance and amount of incident light in crystalline silicon solar cell. In this study, electrode was formed by screen printing method with various conditions like squeegee angle, printing speed, snap off, printing pressure. After optimizing various conditions, double printing method was applied to obtain low series resistance and high aspect ratio. As a result, we obtained electrode resistance 45.31 ohm, aspect ratio 4.38, shading loss 7.549% mono-crystalline silicon solar cell with optimal double screen printing condition.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.134.2-134.2
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• 2017

최근 고성능, 저 전력 반도체 소자를 위한 미세 공정 기술이 발전함에 따라, gate oxide의 두께 및 선폭이 감소하고, aspect ratio가 증가하고 있는 추세이다. 따라서 얇아진 gate oxide를 통한 채널 물질로의 boron 확산을 막기 위한 고농도 질화 막 증착의 필요성이 높아지고 있으며, high aspect ratio의 gate oxide에 적용 가능한 우수한 step coverage의 질화막 또한 요구되고 있다. 이러한 요구조건을 만족시키기 위해 일반적인 13.56MHz의 플라즈마 소스를 이용한 질화연구들이 선행되어져 왔으나, 높은 binding energy(~24 eV)를 가지고 있는 N2 molecule gas를 효과적으로 dissociation 하지 못해 충분한 질화공정이 수행되어질 수 없었을 뿐만 아니라 높은 공정온도($>200^{\circ}C$에서 진행되어 반도체소자에 손상을 줄 수 있다. 본 연구에서는 이러한 문제들을 해결하기 위해 VHF (162MHz)를 이용한 플라즈마를 통해 고밀도에서 낮은 전자온도와 높은 진동온도의 플라즈마를 구현하여 20%이상의 높은 질화율을 얻을 수 있었고, multi-tile push-pull 플라즈마 소스를 통해 VHF 사용 시 나타나는 standing wave effect를 제어하여 high aspect ratio의 gate sidewall spacer에 우수한 step coverage의 질화막을 형성시킬 수 있었다.