• Journal of Korean Vacuum Science & Technology
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• v.6 no.3
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• pp.120-125
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• 2002

The aim of the present work is to optimized the annealing parameter in both front and back screen printed contacts realization on p-type multicrystalline silicon and with phosphorus diffused. The RTA treatments were carried out at various temperatures from 600 to 850$\^{C}$ and annealing time ranging from 3 min to 5 min in air, O$_2$and N$_2$ ambiance. The contacts parameters are obtained according to Transmission Line Model measurements. A good RTA cycle is obtained with a temperature plateau of 700$\^{C}$-750$\^{C}$ and annealing ambiance of air. Several processing parameters required for good cell efficiency are discussed with an emphasis placed on the critical role of the glass frit in the aluminum paste. A anamolus behaviour of Aluminum n-doping on p-type Si wafer, contact at high temperature have also been studied.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.292-292
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• 2014

Wide band gap semiconductors, such as III-nitrides (GaN, AlN, InN, and their alloys), SiC, and diamond are expected to play an important role in the next-generation electronic devices. Specifically, GaN-based high electron mobility transistors (HEMTs) have been targeted for high power, high frequency, and high temperature operation electronic devices for mobile communication systems, radars, and power electronics because of their high critical breakdown fields, high saturation velocities, and high thermal conductivities. For the stable operation, high power, high frequency and high breakdown voltage and high current density, the fabrication methods have to be optimized with considerable attention. In this study, low ohmic contact resistance and smooth surface morphology to AlGaN/GaN on 2 inch c-plane sapphire substrate has been obtained with stepwise annealing at three different temperatures. The metallization was performed under deposition of a composite metal layer of Ti/Al/Ni/Au with thickness. After multi-layer metal stacking, rapid thermal annealing (RTA) process was applied with stepwise annealing temperature program profile. As results, we obtained a minimum specific contact resistance of $1.6{\times}10^{-7}{\Omega}cm2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.10-11
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• 2006

In this study, the Ni/Co/TiN (6/2/25 nm) structure was deposited for thermal stability estimation. Vacuum (30 mTorrs) annealing was carried out to compare with furnace annealing in nitrogen ambient. The proposed Ni/Co/TiN structure exhibited low temperature silicidation and wide range of rapid thermal process (RTP) windows. The sheet resistance was too high to measure after furnace annealing at $600^{\circ}C$ due to the thin thickness (15 nm) of the nickel silicide. However, the sheet resistance maintained stable characteristics up to $600^{\circ}C$ for 30 min after vacuum annealing. Therefore, the low resistance of thin film nickel silicide was obtained by vacuum annealing at $600^{\circ}C$.

• Journal of Korean Vacuum Science & Technology
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• v.4 no.2
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• pp.50-54
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• 2000

We studied the synthesis of S $i_{1-x}$ Cx (x=0.016) epitaxial layer using ion implantation and solid phase epitaxy (SPE). The activation energy Ea was obtained for the loss of substitutional carbon using fourier transform-infrared spectroscopy (FTIR) and high-resolution x-ray diffraction (HR-XRD). In FTIR analysis, the integrated peak intensity was used to quantify the loss of carbon atoms from substitutional to interstitial sites during annealing. The substitutional carbon contents in S $i_{0.984}$ $C_{0.016}$ were also measured using HR-XRD. By dynamic simulations of x-ray rocking curves, the fraction of substitutional carbon was obtained. The effects of annealing temperature and time were also studied by comparing vacuum furnace annealing with rapid thermal annealing (RTA))))))

• Korean Journal of Optics and Photonics
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• v.11 no.3
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• pp.152-157
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• 2000

Post-deposition vacuum annealing effects in electron-bearn-evaporated indium tin oxide (ITO) films have been investigated by the change of transmittance, sheet resistance and crystalline structure with annealing temperature ( $200-335^{\circ}C$) and oxygen partial pressure ($1\times^10^{-5}-1$\times10^{-4} torr$) in air and vacuum. The sarnples were polycrystalline films with a preferred orientation in the (222) plan. High quality films with sheet resistance as low as 62 Q/O and transmittance over 99% (absentee layer at 500 nm) have been obtained by suitably controlling the vacuum annealing pararneters.neters.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• Journal of the Korean Vacuum Society
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• v.4 no.S2
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• pp.115-130
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• 1995

In order to produce Cu nanocrystallite in silicon wafer, the implantation technique was used. The samples of silicon (100) wafers were implanted by $Cu^+$ ions at 100 keV and with varying the doses at room temperature. Post-annealing was performed at $800^{\circ}C$ with Ar environment. To investigate the formation of Cu nanocrystallite with ion doses and growth process by thermal annealing, SIMS and HRTEM(high resolution transmission electron microscopy)spectra were studied.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.102-102
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• 1999

Visible photoluminescence(PL) in si-implanted SiO2 films on crystaline silicon were observed. Thermal oxide films of 1 ${\mu}{\textrm}{m}$ thickness on P-type crystal silicon were made and si+ ions were implanted with 200keV acceleration voltage on ti. Argon laser (wavelength 488nm) and PM tube were used for PL measurements. As annealing time increased at low temperature, the visible PL intensity are increased and the peak positions are changed. On the other hand, with increasing annealing time at high temperature, the visible PL intensity are disappeared. From the PL peaks and intensity changes, XRD results, and TEM observations, we will discuss the origin of PL in Si+-implanted SiO2 films with oxygen righ defects and silicon rich defects.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.140.1-140.1
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• 2013

The native silicon-oxide (SiOx) layer at the metal/Silicon interface acts as an electrical resistance to the metal contact of devices. Various methods are proposed for removing this layer, such as sputtering before metal contact formation or high temperature annealing. We studied the chemical evolution of the Au/SiOx/Si system during the annealing at $500^{\circ}C$ using a spatially resolved photoelectron emission method. Scanning photoelectron emission microscopy (SPEM) and core level spectra from local area of the sample show the inhomogeneous oxidation and formation of silicide of Au, as well as valence band spectra reveals the role of Au atoms during the dissociation process of SiOx.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.168-173
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• 2003

Recently, according to the rapid progress in Flat-panel-display industry, there has been a growing interest in the poly-Si process. Compared with a-Si, poly-Si offers significantly high carrier mobility, so it has many advantages to high response rate in Thin Film Transistors (TFT's). We have investigated a new process for the high temperature Solid Phase Crystallization (SPC) of a-Si films without any damages on glass substrates using thin film heater. because the thin film heater annealing method is a very rapid thermal process, it has very low thermal budget compared to the conventional furnace annealing. therefore it has some characteristics such as selective area crystallization, high temperature annealing using glass substrates. A 500 $\AA$-thick a-Si film was crystallized by the heat transferred from the resistively heated thin film heaters through $SiO_2$ intermediate layer. a 1000 $\AA$-thick $TiSi_2$ thin film confined to have 15 $\textrm{mm}^{-1}$ length and various line width from 200 to 400 $\mu\textrm{m}$ was used as the thin film heater. By this method, we successfully crystallized 500 $\AA$-thick a-Si thin films at a high temperature estimated above $850^{\circ}C$ in a few seconds without any thermal deformation of g1ass substrates. These surprising results were due to the very small thermal budget of the thin film heaters and rapid thermal behavior such as fast heating and cooling. Moreover, we investigated the time dependency of the SPC of a-Si films by observing the crystallization phenomena at every 20 seconds during annealing process. We suggests the individual managements of nucleation and grain growth steps of poly-Si in SPC of a-Si with the precise control of annealing temperature. In conclusion, we show the SPC of a-Si by the thin film heaters and many advantages of the thin film heater annealing over other processes