• Title/Summary/Keyword: high speed mode

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Sliding Mode Control using Neural Network for a Robot Manipulator (로봇 매니플레이터를 위한 신경회로망을 이용한 슬라이딩 모드 제어)

  • 박양수;박윤명;최부귀
    • Journal of the Institute of Convergence Signal Processing
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    • v.2 no.2
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    • pp.89-94
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    • 2001
  • The position control accuracy of a robot manipulator is significantly deteriorated when a long arm robot is operated at a high speed. This paper presents a very simple sliding mode control which eliminates multiple mode residual vibration in a robot manipulator. The neural network is used to avoid that sliding mode condition is deviated due to the change of system parameter and disturbance. This paper is suggested control system which designed by sliding mode controller using neural network. The effectiveness of proposed scheme is demonstrated through computer simulation.

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An Experimental Study of T-mode Vibration on the Diesel Power Plant (디젤 발전소의 T-mode 진동에 관한 실험적 고찰)

  • Lee, D.C.;Nam, T.K.;Bae, Y.C.;Kim, Y.H.
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2005.11a
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    • pp.411-416
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    • 2005
  • Nowadays, diesel power plant using low speed two stroke diesel engine is widely used in islands and restricted areas. Considerations were given to its benefit of high thermal efficiency, reliability and durability compared to the other prime movers. However, various types of engine vibration affect neighboring buildings to their structural vibration. For this, diesel power plant are held liable for the troubles caused by these vibration. These are mainly due to the X- and H-type engine vibrations which we excited by the X- and H- guide force moment. Authors have identified a structural vibration of new pattern called ‘T-mode vibration’ due to the torsional vibration of shafting system. In this paper, T-mode vibration is analyzed through an experimental method based on the global vibration measurement.

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Reliability of Sn-Ag-Cu Solder Joint on ENEPIG Surface Finish: 2. Effects of time of Pd activation (ENEPIG 표면처리에서의 Sn-Ag-Cu 솔더조인트 신뢰성: 2. Pd 촉매 시간의 영향)

  • Huh, Seok-Hwan;Lee, Ji-Hye;Ham, Suk-Jin
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.3
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    • pp.51-56
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    • 2014
  • The reliability of solder joint is significantly affected by the property of surface finish. This paper reports on a study of high speed shear energy and failure mode for Sn-4.0wt%Ag-0.5wt%Cu (SAC405) solder joints with the time of Pd activation. The nodule size of electroless Ni-P deposit increased with increasing the time of Pd activation. The roughness (Ra) of electroless Ni-P deposit decreased with increasing the time of Pd activation. Then, with $HNO_3$ vapor, the quasi-brittle and brittle mode of SAC405 solder joint decreased with increasing the time of Pd activation. This results indicate that the increase in the Pd activation time for Electroless Ni/ Electroless Pd/ Immersion Au (ENEPIG) surface finish play a critical role for improving the robustness of SAC405 solder joint.

Recent Trends in System-Level EMC Investigation and Countermeasure Technology for RF Interference Due to High-Speed Digital System Noise (고속 디지털 시스템 잡음에 의한 RF 시스템 간섭(RFI) 현상에 관한 시스템 레벨의 EMC 분석 및 대책 기술 연구 동향)

  • Koo, Tae-Wan;Lee, Ho Seong;Yook, Jong-Gwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.10
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    • pp.966-982
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    • 2014
  • This paper presents recent trends in system-level EMC investigation and countermeasure technology for radio frequency interference (RFI) influenced by noise generated in high-speed digital system. Recently, as the only digital device can perform various roles, there are a variety of EMI/EMC problems between systems. Especially, RFI is now recognized as a major problem, which occurs by EMI caused by the digital system. Therefore, in this paper, recent trends of RFI investigation from component-level to system-level are introduced and analyzed. Furthermore, in order to solve the RFI problem, recent researches are presented and investigated for the occurrences and suppression methods of common-mode noise which is one of the major noise sources in high-speed digital system. Lastly, this paper suggested future research of system-level EMC analysis and countermeasure technology for RFI problems.

The Characteristics of Efficiency and Torque in $L_1-B_8$ mode USM Having Linear Movement (선형 운동하는 $L_1-B_8$ 모드 초음파 전동기의 효율과 토크 특성)

  • U, Sang-Ho;Shin, Soon-In;Kim, Jin-Soo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07b
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    • pp.585-588
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    • 2002
  • The USM uses friction between a mobile part (rotor) and a vibration part(stator), which is different from the principle of the conventional motor based on the interaction of electric and magnetic fields. In this thesis, a flat-type $L_1-B_8$ mode USM was designed and fabricated the characteristics of an ultrasonic vibration. The results of fabricated USM are as follows: (1) In case of ultrasonic motor with elastic-body of stainless, when applied voltage, frequency, pressing force of rotor were 50 [V], 27.9 [kHz], 1.5 [N], 5.0[mN m] respectively, the speed of revolution could be presented up to 0 [cm/s]. (2) In case of ultrasonic motor with elastic-body of brass, when applied voltage, frequency, pressing force of rotor were 50 [V], 21.4 [kHz], 1.5 [N], 1.4[mN m]respectively, the speed of rotor revolution was presented up to 0 [cm/s]. (3) The USM of elastic-body of stainless showing 1.17[%], somewhat low, in the maximum efficiency according to torque was superior to the USM of elastic-body of brass showing 0.34 [%]. The Flat-type $L_1-B_8$ mode USM had characteristics of typical drooping torque-speed, large torque and high speed, and operating in both directions by phase reversal.

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Spaceborne Data Link Design for High Rate Radar Imaging Data Transmission (고속 레이다 영상자료 전송을 위한 위성탑재 데이터 링크 설계)

  • Gwak, Yeong-Gil
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.3
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    • pp.117-124
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    • 2002
  • A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution because of the strict requirement for the real-time data transmission of the massive SAR data in a limited time of mission. In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath. The designed data link module can be effectively used for the spaceborne and airborne applications which requires to expand the high speed data link capability.

A Dual-Mode 2.4-GHz CMOS Transceiver for High-Rate Bluetooth Systems

  • Hyun, Seok-Bong;Tak, Geum-Young;Kim, Sun-Hee;Kim, Byung-Jo;Ko, Jin-Ho;Park, Seong-Su
    • ETRI Journal
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    • v.26 no.3
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    • pp.229-240
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    • 2004
  • This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

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A Study of Design and Analysis on the High-Speed Serial Interface Connector (고속 직렬 인터페이스 커넥터의 설계 및 분석에 대한 연구)

  • Lee, Hosang;Shin, Jaeyoung;Choi, Daeil;Nah, Wansoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.12
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    • pp.1084-1096
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    • 2016
  • This paper presents method of design and analysis of a high-speed serial interface connector with a data rate of 12.5 Gbps. A high-speed serial interface connector is composed of various material and complex structures. It is very difficult to match the impedance of each discontinuous portion of connector. Therefore, this paper proposes the structure of a connector line that be simplified a connector. In the structure of proposed connector line, this research presents a method for extracting R, L, C and G parameters, analyzing the differential mode impedance, and minimizing the impedance discontinuity using time domain transmissometry and time domain reflectometry. This paper applies the proposed methods in the connector line to the high-speed serial interface connector. The proposed high-speed serial interface connector, which consists of forty-four pins, is analyzed signal transmission characteristics by changing the width and spacing of the four pins. According to the analysis result, as the width of the ground pin increases, the impedance decreases slightly. And as the distance between the ground pin and the signal pin increases, the impedance increases. In addition, as the width of the signal pin increases, the impedance decreases. And as the distance between the signal pin and the signal pin increases, the impedance decreases. The impedance characteristic of initial connector presents ranges from 96 to $139{\Omega}$. Impedance characteristic after applying the structure of proposed connector is shown as a value between 92.6 to $107.5{\Omega}$. This value satisfies the design objective $100{\Omega}{\pm}10%$.

Air Pollutant Emission Characteristics of a Light Duty Diesel Vehicle Affected by Road Infrastructure Improvement and Traffic flow Changes (도로 기반시설 개선과 교통흐름 변화에 따른 소형 경유자동차의 대기오염물질 배출특성)

  • keel, Jihoon;Lee, Taewoo;Lee, Sangeun;Jung, Sungwoon;Yun, Boseop;Kim, Jeongsoo;Choi, Kwangho
    • Journal of ILASS-Korea
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    • v.21 no.4
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    • pp.214-222
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    • 2016
  • Changes in road infrastructure affect driving patterns and pollutant emission characteristics. we analyzed the changes in driving patterns and pollutant emission characteristics of the driving route via measured driving patterns at year 2009 and 2016. Since 2009, there has been an increase in population and traffic demand, including residential areas and industrial facilities. Traffic conditions were improved such as the opening of the highway Inter-Change to Seoul and the construction of underground driveway. As a result, the average vehicle speed increased. More detail comparisons have made on the changes of the underground driveway section and the crossroad section, which are expected to have significant changes in the transportation infrastructure. The vehicle speed distribution of the underground driveway changed from low speed to high speed, and the increase of the time spent at the high speed and high load caused the increase of NOx emissions. The vehicle speed also increased at the crossroad section, and the consequence NOx and $CO_2$ emissions decreased. It is mainly because the decreased time spent at idle, which results from the proper traffic demand management at this area.

A Design of the High-Speed Cipher VLSI Using IDEA Algorithm (IDEA 알고리즘을 이용한 고속 암호 VLSI 설계)

  • 이행우;최광진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.1
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    • pp.64-72
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    • 2001
  • This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.