• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제53권12호
• /
• pp.751-758
• /
• 2004

This paper presents a new method to compensate the non-linearity for matrix converter drives using PQR instantaneous Power theory. The non-linearity of matrix converter drives such as commutation delay, turn-on and turn-off time of switching device, and on-state switching device voltage drop is modelled by PQR power theory and compensated using a reference current control scheme. The proposed method does not need any additional hardware and off-line experimental measurements. The proposed compensation method is applied for high performance induction motor drives using a 3 kW matrix converter system without a speed sensor. Simulation and experimental results show the proposed method using PQR power theory Provides good compensating characteristic.

• 한국항행학회논문지
• /
• 제18권3호
• /
• pp.229-235
• /
• 2014

본 논문은 고효율 고선형 특성을 얻기 위하여 신테라사가 제공한 디지털로 제어되는 아날로그 전치왜곡 칩을 이용한 도허티 전력증폭기를 설계하였다. 여기서 사용된 아날로그 전치왜곡기는 입력과 출력신호를 비교하여 출력의 혼변조 신호 특성을 개선하기 위하여 입력 신호의 크기와 위상을 조절함으로서 선형성을 개선시켰다. 또한, 도허티 전력증폭기를 설계하여 이용함으로써 고효율의 특성을 얻었다. 제작된 전력증폭기는 중심주파수 2150 MHz에서 평형증폭기와 비교하여 11% 이상의 효율 개선 효과와 출력 전력 100W 이하에서 인접채널 전력을 15 dB 이상 개선시켰다.

• Nuclear Engineering and Technology
• /
• 제55권2호
• /
• pp.484-492
• /
• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• ETRI Journal
• /
• 제31권5호
• /
• pp.576-584
• /
• 2009

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

• Journal of information and communication convergence engineering
• /
• 제15권2호
• /
• pp.112-116
• /
• 2017

In this work, we demonstrated a low noise and high linearity low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with novel active bias circuit for LTE applications. The device technology used in this work relies on a process involving a $0.25-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (PHEMT). The LNA MMIC with a novel active bias circuit has a small signal gain of $19.7{\pm}1.5dB$ and output third order intercept point (OIP3) of 38-39 dBm in the frequency range 1.75-2.65 GHz. The noise figure (NF) is less than 0.58 dB over the full bandwidth. Compared with the characteristics of the LNA MMIC without using the novel active bias circuit, the OIP3 is improved about 2-3 dBm. The small signal gain and NF showed no significant change after using the active bias circuit. The novel active bias circuit indeed improves the linearity performance of the LNA MMIC without degradation.

• 전기학회논문지
• /
• 제64권3호
• /
• pp.433-437
• /
• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권1호
• /
• pp.100-108
• /
• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• IEIE Transactions on Smart Processing and Computing
• /
• 제3권4호
• /
• pp.161-166
• /
• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• 한국전자파학회논문지
• /
• 제16권11호
• /
• pp.1059-1066
• /
• 2005

본 논문은 피드포워드 전력 증폭기의 효율 개선을 위한 도허티 증폭기의 적용에 관한 연구이다. 성능 분석을 위하여 중심 주파수 2.14 GHz의 WCDMA 4FA신호를 인가하여 평균 출력 전력 15 W에서 측정하였다. 적용한 도허티 증폭기는 동급 class AB 증폭기와 비교하여 고효율 저선형성의 특성을 나타내며 효율 개선을 위하여 피드포워드 전력 증폭기(FPA)의 주 증폭기로 사용되었다. 특성 변화를 분석하기 위해 선형성과 효율 특성이 다른 2가지 종류의 도허티 증폭기를 적용하였으며 각각의 FPA들은 평균 출력 15 W에서 효율은 $2\%$ 이상의 개선을 보였지만 선형성은 1.5 dBc 이상 저하되는 특성을 나타냈다. 저하된 선형성을 개선하기 위하여 부가적으로 오차 루프의 결합 계수(CF)와 오차 증폭기의 용량을 변화시켰다. CF와 오차 증폭기의 용량 변화로 효율 개선과 높은 선형성을 얻을 수 있었고 도허티 증폭기가 35 dBc 이상의 선형성을 유지하면 부가적인 변화 없이 평균 출력 전력 15 W에서 $2\%$ 이상의 효율 개선과 충분한 선형성을 얻을 수 있다.

• 한국전자파학회논문지
• /
• 제19권8호
• /
• pp.807-813
• /
• 2008

본 논문에서는 선형성 증가를 위해 도허티 증폭기의 게이트 바이어스를 조정하는 방식을 제시하였다. 도허티 증폭기의 선형성 향상은 출력 결합 지점에서의 고조파 상쇄를 통해 이루어진다. 하지만 고조파의 상쇄는 그 크기와 위상이 출력 지점에서 같은 크기와 서로 다른 위상을 가지고 있어야 이루어질 수 있는데, 넓은 출력 전력 범위에서 위와 같은 조건을 만족시키는 것은 쉽지 않다. 선형성 증가를 위해 도허티 증폭기의 캐리어 증폭기와 피킹 증폭기의 선형성 특성을 입력 전력과 각 증폭기의 게이트 바이어스를 조정함으로써 살펴보았다. 살펴본 특성을 기본으로 하여 고조파 상쇄 전력 범위를 증가시키기 위해, 각 전력 레벨에 맞는 게이트 바이어스를 증폭기에 인가하였다. 게이트 바이어스 제어를 통한 선형성 향상을 알아보기 위해, 2.345 GHz에서 Eudyna사의 10-W PEP GaN HEMT EGN010MK 소자를 이용하여 도허티 전력 증폭기를 설계하였고, $P_{1dB}$로부터 10 dB back-off 지점인 33 dBm에서 고효율과 고선형성을 위해 최적화 되었다. WCDMA 1-FA 신호에 대해 제안된 게이트 바이어스 컨트롤 된 도허티 증폭기는 2.8 dB의 선형성 개선을 확인할 수 있었으며, 26 %의 PAE를 확인할 수 있었다. 또한, 802.16-2004 신호에 대해 RCE가 2 dB 증가됨을 확인할 수 있었다.