• 정보과학회 논문지
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• 제44권3호
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• pp.223-231
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• 2017

본 논문에서는 최근 광범위하게 사용되고 있는 멀티 코어 환경에서의 모바일 장치의 성능에 대하여 연구하였다. 이전에 연구되어왔던 멀티 코어의 성능에 대한 분석은, 대부분 데스크톱 PC에서의 분석이었고, heterogeneous 멀티 코어에 대한 분석방법이 충분하지 않았다. 이러한 문제점을 보완하고자 homogeneous 멀티 코어의 분석 방법을 응용한 heterogeneous 멀티 코어 환경에서 성능을 분석하는 방법을 제안하였다. 본 연구에서는 이를 분석하는 데 있어서 작업의 할당에는 Size Interval Task Allocation (SITA) 기법을 사용하였고, 코어에서의 처리 방법은 Shortest Remaining Processing Time (SRPT) 기법을 사용하였다. 이 중 SITA 기법에서 가장 중요한 분석인 cutoff point에 대한 새로운 계산 방법을 제안하였고, 이를 체류 시간을 계산하는 데 사용함으로써 계산의 용이성과 정확성을 높였다. 또한, ESESC 시뮬레이터에서의 측정을 통해 분석값과 측정값에 큰 차이가 없음을 확인하였다.

• 한국인터넷방송통신학회논문지
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• 제18권3호
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• pp.111-117
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• 2018

서로 다른 기능을 가진 코어들을 집적시킨 이기종 다중코어 환경은 더욱 복잡하고 다양해지는 임베디드 시스템의 요구사항들을 만족시키는 강력한 도구이며 특화된 응용을 위해 상이한 코어 상에서 별개의 운영체제를 수행하여 적합한 환경을 구성한다. 그러나 이런 이질성은 개발 환경을 더욱 복잡하게하고 프로그래밍을 어렵게 하며 개발과 디버깅을 쉽지 않도록 만든다. 본 논문에서는 이기종 다중코어 환경을 단일 다중코어 환경으로 매핑 가능함을 보이고 이기종 다중코어 환경에서 프로세스 간 통신에 사용하는 RPMsg를 리눅스 기반으로 구축하여 여러 단계의 개발과정을 축소할 수 있음을 보인다. 이러한 단순화를 통해 이기종 다중코어 환경에서의 개발 기간을 대폭 줄여줄 수 있는 시뮬레이션 방법을 제안한다.

• 대한임베디드공학회논문지
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• 제17권6호
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• pp.375-382
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• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• IEIE Transactions on Smart Processing and Computing
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• 제5권4호
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• pp.289-293
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• 2016

As more mobile devices are equipped with multi-core CPUs and are required to execute many compute-intensive multimedia applications, it is important to optimize the systems, considering the underlying parallel hardware architecture. In this paper, we implement and optimize ray-tracing application tailored to a given mobile computing platform with multiple heterogeneous processing elements. In this paper, a lightweight ray-tracing application is specified and implemented in Kahn process network (KPN) model-of-computation, which is known to be suitable for the description of real-time applications. We take an open-source C/C++ implementation of ray-tracing and adapt it to KPN description in the Distributed Application Layer framework. Then, several possible configurations are evaluated in the target mobile computing platform (Exynos 5422), where eight heterogeneous ARM cores are integrated. We derive the optimal degree of parallelism and a suitable distribution of the replicated tasks tailored to the target architecture.

• 대한임베디드공학회논문지
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• 제9권6호
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• pp.315-321
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• 2014

Mobile computing devices such as smartphones, tablet computers have become the dominant personal computing platforms. Energy efficiency is a prime design requirement for smart devices. In order to reduce the energy consumption of the smart devices, analysis of performance and energy consumption has become important. However, so far, there is no framework for the analysis and systematic approach to improve the power consumption of the heterogeneous multi-core system. In this paper, we describe a new framework for the analysis of heterogeneous multi-core systems. Also, by use of an analysis tool, can be provide reliability and productivity of development results.

• Nuclear Engineering and Technology
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• 제55권6호
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• pp.2112-2124
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• 2023

With the rise of economic and safety standards for nuclear reactors, new concepts of Gen-IV reactors and modular reactors showed more complex designs that challenge current tools for reactor physics analysis. A Monte Carlo (MC) two-step method was proposed in this work. This calculation scheme uses the continuous-energy MC method to generate multi-group cross-sections from heterogeneous models. The multi-group MC method, which can adapt locally-heterogeneous models, is used in the core calculation step. This calculation scheme is verified using a Gen-IV modular lead-based fast reactor (LFR) benchmark case. The influence of homogenized patterns, scatter approximations, flux separable approximation, and local heterogeneity in core calculation on simulation results are investigated. Results showed that the cross-sections generated using the 3D assembly model with a locally heterogeneous representation of control rods lead to an accurate estimation with less than 270 pcm bias in core reactivity, 0.5% bias in control rod worth, and 1.5% bias on power distribution. The study verified the applicability of multi-group cross-sections generated with the MC method for LFR analysis. The study also proved the feasibility of multi-group MC in core calculation with local heterogeneity, which saves 85% time compared to the continuous-energy MC.

• 한국멀티미디어학회논문지
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• 제22권7호
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• pp.759-769
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• 2019

Since a surgery simulation should be able to represent the internal structure of the human body, it is advantageous to adopt volume based techniques rather than polygon based techniques. However, the volume based techniques induce large computation to deform heterogeneous volume datasets such as bones and muscles. In this study, we propose a new method to deform volume data using multi-core CPUs. By improving previous studies, the proposed method minimizes unnecessary propagation operations. Moreover, we propose an efficient task-partitioning method for volume deformation using multi-core CPUs. As a result, we can simulate the deformation of heterogeneous volume data at an interactive speed without special hardware.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권6호
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• pp.2648-2668
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• 2016

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

• 한국산업정보학회논문지
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• 제27권6호
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• pp.69-75
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• 2022

본 논문에서 비대칭 멀티 코어 구조의 스마트 모바일 단말에서 실시간성 보장과 에너지 소비량 절감을 고려한 작업 스케쥴링 기법을 제안한다. 최근 VR, AR, 3D 등 고성능 응용프로그램은 실시간과 고수준 작업이 요구된다. 스마트 단말은 배터리에 의존적이므로 높은 에너지 효율을 위해서 big.LITTLE 구조가 적용되었지만, 이를 제대로 활용하지 못함으로써 에너지 절감효과가 반감되는 문제점이 있었다. 본 논문에서는 big.LITTLE 구조의 단말에서 실시간성과 높은 에너지 효율을 높일 수 있는 비대칭 멀티코어 할당 기법을 제안한다. 이 기법은 SVM 모델을 활용해서 실제 작업의 실행시간을 예측하고 이를 통해서 에너지 소모와 실행시간을 최적화한 알고리즘을 제안한다. 상용 스마트폰에서의 비교실험을 통하여 제안기법이 기존 기법과 유사한 실행시간을 보장하면서 에너지 소비량의 절감을 보였다.

• 한국항행학회논문지
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• 제14권1호
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• pp.57-65
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• 2010

본 연구에서는 새로운 형태의 로봇 제어기의 구조인 이기종 멀티프로세서 제어기의 개념적인 구조를 제시하며, 제어기 내에 분산된 멀티프로세서들을 sRIO 통신을 이용하여 통합하는 구조적인 방법을 소개한다. 또한 sRIO 통신으로 통합된 이기종 멀티프로세서의 구현을 위한 방법으로 FPGA 내에 설계된 sRIO IP Core를 활용한 시뮬레이션을 수행하고 그 결과를 확인하였다.