• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.401-408
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• 2001

This paper shows the design, fabrication and performance analysis of VCO which plays a major role in 5.8 GHz RF module for ITS. The design specifications of the VCO are determined on the basis of 5.8 GHz RF modul performance requirements. The design parameters are optimized through ADS simulation tool. The operating characteristic and performance analysis of the implemented VCO based on the design parameters are accomplished. The frequency variations according to the voltage change(0 ~5 V) of varactor diode are from 5.42 GHz to 5.518 GHz and the power level is 6.5 dBm. The second harmonic suppression are -21.5 dBc at 5.51 GHz and the phase noise characteristics are -83.81 dBc at 10 kHz offset frequency. The implemented VCO is available to not only DSRC and also, 5.8 GHz other systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.335-344
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• 2004

A low phase noise EQM(Engineering Qualified Model) LO(Local Oscillator) has been developed for Ka-band satellite transponder. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is also designed using a high impedance inverter coupled with dielectric resonator to improve the phase noise performances out of the loop bandwidth. The mechanical analysis fur housing and the thermal analysis fur circuit board are achieved. This EQM LO is applied to Ka-band satellite transponder of EQM level after environmental experiments for space application. The LO has the harmonic suppression characteristics above 52 ㏈c and requires low power consumption under 1.3 watts. The phase noise characteristics are exhibited as -101.33 ㏈c/㎐ at 10 ㎑ offset frequency and -114.33 ㏈c/㎐ at 100 ㎑ offset frequency, with the output power of 14.0 ㏈m${\pm}$0.17 ㏈ over the temperature range of -15∼＋65$^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.9
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• pp.55-59
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• 2008

In this paper, the linearity of Doherty amplifier has been improved by applying a compact slow-wave microstrip branch-line coupler on the output of Doherty amplifier. The proposed branch coupler has four microstrip high-low impedance resonant cells periodically placed inside the branch-line coupler to result in high slow-wave effect. The new coupler not only effectively reduces the occupied area to 30% of the conventional branch-line coupler at 1.8GHz, but also has high second harmonic suppression performance. We obtained the 3rd-order intermodulation distortion ($IMD_3$) of -31.16 dBc for CDMA applications with that of maintaining the constant power added efficiency (PAE). The IMD3 performance is improved as much as -7 dBc compared with a Doherty amplifier.

• Journal of Navigation and Port Research
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• v.30 no.10 s.116
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• pp.847-853
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• 2006

In this paper, we designed VCO(voltage controlled oscillator} that is composed of a dielectric resonator and a varactor diode, and the PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The results at 12.05 GHz show the output power is 13.54 dBm frequency tuning range approximately +/- 7.5 MHz, and power variation over the tuning range less than 0.2 dB, respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 dBc/Hz at 100 kHz offset from carrier, and The second harmonic suppression is less than -41.49 dBc. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.7
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• pp.739-747
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• 2007

Dual-mode bandpass filter was designed by using periodic stepped impedance ring resonator with step perturbation. The periodic stepped impedance ring resonator has the effects of size reduction and $2^{nd}$ harmonic suppression by changing characteristic impedance ratio. The perturbation for dual-mode generation was also easily controlled by characteristic impedance ratio, and the variation of dual-mode resonant frequencies and attenuation pole frequencies were analyzed by the effect of step perturbation. Chip capacitors were used for input/output coupling, and the variation of center frequency by the coupling capacitance and step perturbation was also considered. From the results, two types of 2 GHz dual-mode bandpass filter were fabricated in size of $14{\times}14mm^2$, those have different attenuation poles and bandwidths. The measured results of proposed bandpass filters showed a good agreement with the calculated estimations, and those have insertion loss of 2.52, 0.52 dB and 3 dB bandwidth of 4.03, 15.02 %, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.126-135
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• 2007

This paper proposes a new miniaturization method for a parallel coupled line filter with enhanced bandwidth characteristics. A previous method incorporated several advantages, such as size reduction through the use of only a small number of capacitors, in addition to grounding, suppression of harmonic characteristics, and improved skirt characteristics for the parallel coupled line filter, which is conventional in the field of RE filters due to its design and fabrication simplicity. However, the previous method also has disadvantages related to the bandwidth shrinkage of the miniaturized filters. In this paper, the amount of bandwidth shrinkage is analyzed in terms of the relationship between the loaded Q(quality factor) and the group delay of a resonator. Moreover, the reduction in the bandwidth is solved by a design with new design equations. To show the validity of the proposed method, a hairpin filter with a center frequency of 5.2 GHz and an fractional bandwidth(FBW) of 10% was scaled down to half its original dimension by the proposed method with the enhanced bandwidth characteristics. The measured result shows a high level of agreement with theoretical results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.