• Journal of information and communication convergence engineering
• /
• v.7 no.3
• /
• pp.399-403
• /
• 2009

In IEEE 802.15.1 (Bluetooth) Ad-hoc networks, the frequency is resolved by the specific part of the digits of the Device clock and the Bluetooth address of the Master device in a given piconet. The piconet performs a fast frequency hopping scheme over 79 carriers of 1-MHz bandwidth. Since there is no coordination between different piconets, packet collisions may occur if two piconets are located near one another. In this paper, we proposed a software/hardware co-design of an adaptive frequency decision mechanism so that more than two different kinds of wireless devices can stay connected without frequency collision. Suggested method was implemented with C program and HDL (Hardware Description Language) and automatically synthesized and laid out. The adaptive frequency hopping circuit was implemented in a prototype and showed its operation at 24MHz correctly.

• KSCE Journal of Civil and Environmental Engineering Research
• /
• v.31 no.4D
• /
• pp.603-611
• /
• 2011

After Kyoto Protocol was adopted for green gas reduction, each nations are stepping up efforts to reduce $CO_2$ of a typical green gas. Construction industry also is trying $CO_2$ reduction with the techniques of two types which are software and hardware techniques. The software technique are Passive Design considered green gas emission and the environment impact assessment by LCA. The hardware techniques are adjustment of equipment system and development of eco- friendly material. But, it is nonexistent that a study related to $CO_2$ emission considered detail process in construction industry. This study analyzed the correlation of equipment combination, $CO_2$ emission and duration by calculate $CO_2$ emission follow to equipment combination on earth-work which is the process emitted most $CO_2$ among railway bedding construction.

• Journal of the Institute of Convergence Signal Processing
• /
• v.11 no.2
• /
• pp.177-182
• /
• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.

• Journal of Positioning, Navigation, and Timing
• /
• v.6 no.1
• /
• pp.1-8
• /
• 2017

In this study, to design a multi-GNSS receiver using single RF front-end, the receiving performances for various frequency plans were evaluated. For the fair evaluation and comparison of different frequency plans, the same signal needs to be received at the same time. For this purpose, two synchronized RF front-ends were configured using USRP X310, and PC-based software was implemented so that the quality of the digital IF signal received at each front-end could be evaluated. The software consisted of USRP control, signal reception, signal acquisition, signal tracking, and C/N0 estimation function. Using the implemented software and USRP-based hardware, the signal receiving performances for various frequency plans, such as the signal attenuation status, overlapping of different systems, and the use of imaginary or real signal, were evaluated based on the C/N0 value. The results of the receiving performance measurement for the various frequency plans suggested in this study would be useful reference data for the design of a multi-GNSS receiver in the future.

• Proceedings of the KIEE Conference
• /
• 1996.07b
• /
• pp.916-918
• /
• 1996

We have an urgent matter that is lack of energy resource. So we have to accomplish the design of economical energy utility systems and to develop energy facilities with high efficiency. Cogeneration system is one of them. It has high efficiency and can solve unbalanced electricity and heat demand in Summer & Winter concurrently. Recently, to increase the efficiency and stability of the total system, it is applying automatic control and monitoring software to the hardware facilities in industrial control systems. Therefore, these systems has been researched and developed in the advanced countries. It also has been researched and developed in the domestic since '60. But the control and monitoring software in cogeneration system has been hardly developed and has been imported expensive products from the advanced countries. In this study, we have developed the software of operating control, status monitoring, operating data managing and tele-controlling. We have confirmed usefullness of developed software by applying to gas turbine cogeneration system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.4
• /
• pp.50-61
• /
• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2007.11a
• /
• pp.779-781
• /
• 2007

Nowadays, as the increasing functionality and scales of embedded systems, system design grows more complex than before. So verification and simulation of systems become an important facet in hardware-software co-design issues. But it is almost impossible to simulate an embedded system without real hardware implementation or environment communication, especially for control-dominated reactive systems. Therefore, in this paper, we will introduce a GUI environment module generator for integrated Esterel\C++ simulation. By generating the GUI modeling environment, we can simulate and verify the whole embedded system conveniently.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.8
• /
• pp.45-52
• /
• 2017

This paper presents a high-performance software-hardware dehazing system based on a dedicated hardware accelerator for the haze removal. In the proposed system, the dedicated hardware accelerator performs the dark-channel-prior-based dehazing process, and the software performs the other control processes. For this purpose, the dehazing process is realized as an OpenCL kernel by finding the inherent parallelism in the algorithm and is synthesized into a hardware by employing a high-level-synthesis technique. The proposed system executes the dehazing process much faster than the previous software-only dehazing system: the performance improvement is up to 96.3% in terms of the execution time.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.66 no.8
• /
• pp.1250-1256
• /
• 2017

In this research, a high-performance ultrasonic positioning system is proposed to track the positions of an indoor mobile object. Composed of an ultrasonic sender (mobile object) and a receiver (anchor), the system employs three ultrasonic time-off-flights (TOFs) and trilateration to estimate the positions of the object with an accuracy of sub-centimeter. On the other hand, because ultrasonic waves are interfered by temperature, wind and various obstacles obstructing the propagation while propagating in air, ultrasonic pulse debounce technique and Kalman filter were applied to TOF and position calculation, respectively, to compensate for the interference and to obtain more accurate moving object position. To perform tasks in real time, ultrasonic signals are processed full-digitally with a Zynq SoC, and as a software design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams. And, a hardware/software co-design is implemented, where the digital circuit portion is designed in the Zynq's fpga and the software portion is c-coded in the Zynq's processors by using the baremetal multiprocessing scheme in which the c-codes are distributed to dual-core processors, cpu0 and cpu1. To verify the usefulness of the proposed system, experiments were performed and the results were analyzed, and it was confirmed that the moving object could be tracked with accuracy of sub-cm.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.39 no.5
• /
• pp.477-485
• /
• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.