• 한국정보통신학회논문지
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• 제19권8호
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• pp.1780-1784
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• 2015

현재의 IP 라우팅은 Layer 3 라우팅 정보를 이용하여 Forwarding시 Destination Address만을 참조하며 Destination-Based Routing Lookup은 모든 Hop에서 필요하다. 따라서 모든 라우터는 Full Internet 라우팅 정보, 약 12만 여개의 라우트 정보를 필요로 할 수 있으며 라우터는 이러한 폭주에 따라 트래픽 부하를 분산 할 수 있는 환경 구성이 필요하다. 본 연구에서는 인터넷 기존망의 고유 특징인 Best Effect 환경에서 대용량 멀티미디어 데이터 전송의 QoS 보장과 하드웨어적 고속 스위칭을 위해 Labeling을 이용하여 packet을 forwarding하는 환경 구성이 필요하다. 데이터 전송을 고성능화하기 위해서 라벨링망의 여러 단계의 정책보다는 프로세스 등 자원 효율화와 단순화 정책이 효과적인지 연구를 통해 알아보며 그 방안으로 일명 lock-up 라벨링망 Header Format으로 고정시켜 단순화된 정책으로 보다 QoS에 효과적인 정책을 적용하는 방법을 고찰한다.

• 한국정보과학회논문지:정보통신
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• 제28권2호
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• pp.262-276
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• 2001

최근들어 특별한 하드웨어나 새 프로토콜의 도움없이 고속 라우터의 포워딩 검색을 지원하는 포워딩 테이블에 대한 연구가 다양하게 진행되고 있다. 본 논문에서는 소프트웨어를 기반으로 일반적인 펜티엄 프로세서에서 기가비트급 포워딩 검색을 지원할 수 있는 새포워딩 테이블 자료구조를 제시한다. 포워딩 검색은 테이블의 크기에 비례해서 복잡도가 증가하는 라우터 성능의 병목지점으로 알려져 있다. 기존의 소프트웨어를 기반으로 하는 포워딩 검색 연구들은 포워딩 테이블 자료구조로 패트리샤 트라이와 그 변형을 이용하거나 프리픽스 길이를 키로 해서 함수를 구성하는 방법등을 사용하여 왔다. 본 논문에서 제안된 포워딩 테이블 자료구조는 라우팅 테이블의 프리픽스를 완전이진 트라이로 구성한후 트라이의 구조와 각 노드별로 링크 되어있는 라우팅 테이블 포인터 정보를 비트열로 표현하여 포워딩테이블을 구성한다. 트라이의 구조와 라우팅 프리픽스 포인터 정보는 배열이나 링크드-리스트로 표현하면 대량의 저장공간을 필요로하지만 제안된 자료구조에서는 각 정보가 하나의 비트로 표현되므로 작은 저장공간으로 충분하며 또한 트라이를 중간 레벨에서부터 검색할 수 있는 방법을 라우팅 테이블을 펜티엄 프로세서의 L2 캐쉬에 저장할 수 있는 작은 크기로 압축하고 검색경로를 단축함으로써 일반적인 펜티엄 프로세서를 이용하여 고속의 포워딩 엔진을 구현할 수 있음을 보여준다. 제안된 방법의 성능을 평가하기 위해서 실제 라우팅 테이블을 대상으로 실험한 결과 초당 5.7백만 번의 라우팅검색성능을 기록하였다.

• 대한전자공학회논문지SD
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• 제46권3호
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• pp.20-25
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• 2009

본 논문에서는 모바일 환경 기반의 3차원 그래픽 연산을 위한 조명처리 엔진 및 쉐이더 프로세서에 사용 가능한 제곱근과 역제곱근 연산기의 구조를 제안한다. 제안하는 구조는 Taylor 전개식을 기반으로 하여 참조 테이블 및 보정 유닛으로 구성되어 있어 참조 테이블의 크기를 줄였다. 연산 결과는 IEEE-754 표준의 단정도 32 bit 부동소수점 형식과 모바일 환경을 위하여 이를 축소한 24 bit 부동소수점 형식에 대해 OpenGL 1.x ES 에서 요구하는 $10^{-5}$의 정확도를 거의 만족한다. 제안된 구조에 따라 설계된 제곱근 및 역제곱근 연산기는 Verilog-HDL을 사용하여 설계되었으며 파라미터 변경을 통하여 24 bit와 32 bit 연산이 가능하도록 합성이 가능하고 1사이클의 잠복기를 갖는다. 설계된 연산기들의 동작은 FPGA를 이용한 검증시스템을 통하여 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.334-337
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• 2001

In this paper we implemented DDFS and gam-phase dectector which use output of DDFS or any sinusoidal signal input to broaden the usability of DDFS. DDFS is composed of a 32 bits phase accumulator, phase increment registers, ROM and several registers for controlling the operations. It generates the digital data for sine wave up to the half of the clock frequency. To reduce the ROM size and increase the speed, we adopt the algorithms based on Taylor's series expansion method. Data at sparse phase intervals are stored in ROM and sine data between intervals are calculated in hardware. Function of Gain-Phase Extraction consists of sine lookup of DDFS and the optimized multipliers.

• 대한핵의학회지
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• 제34권6호
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• pp.439-444
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• 2000

PACS (Picture Archiving and Communication System) is being rapidly spread and installed in many hospitals, but most of the system do not include nuclear medicine field. Although additional costs of hardware for nuclear medicine PACS is low, the complexity in developing viewing software and little market have made the nuclear medicine PACS not popular. Most PACS utilize DICOM 3.0 as standard format, but standard format in nuclear medicine has been Interfile. Interfile should be converted into DICOM format if nuclear images are to be stored and visualized in most PACS. Nowadays, many vendors supply the DICOM option in gamma camera and PET. Several hospitals in Korea have already installed nuclear PACS with DICOM, but only the screen captured images are supplied. Software for visualizing pseudo-color with color lookup tables and expressing with volume view should be developed to fulfill the demand of referring physicians and nuclear medicine physicians. PACS is going to integrate not only radiologic images but also endoscopic and pathologic images. Web and PC based PACS is now a trend and is much compatible with nuclear medicine PACS. Most important barrier for nuclear medicine PACS that we encounter is not a technical problem, but indifference of investor such as administrator of hospital or PACS. Now it is time to support and invest for the development of nuclear medicine PACS.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 춘계학술대회
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• pp.115-117
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• 2022

화이트박스 암호 기법은 암호 키 정보를 소프트웨어 기반 암호화 알고리즘에 섞어 암호 키의 노출을 막는 방식이다. 화이트박스 암호 기법은 허가되지 않은 역공학 분석으로 메모리에 접근하여 기밀 데이터와 키를 유추하기 어렵게 만들어서 종래의 하드웨어 기반의 보안 암호화 기법을 대체하는 기술로 주목받고 있다. 하지만, 암복호화 과정에서 연산 결과와 암호 키를 숨기기 위해 크기가 큰 룩업테이블을 사용하기 때문에 암복호 속도가 느리고, 메모리 사이즈가 커지는 문제가 발생한다. 특히 최근 저가, 저전력, 경량의 사물인터넷 제품들은 제한된 메모리 공간과 배터리 용량 때문에 화이트박스 암호을 적용하기 어렵다. 또한, 실시간 서비스를 지원해야 하는 네트워크 환경에서는 화이트박스 암호의 암복호화 속도로 인해 응답 지연 시간이 증가하여 통신 효율이 열화된다. 따라서 본 논문에서는 S.Chow가 제안한 AES 기반 화이트박스(WBC-AES)를 사용하여 속도와 메모리 요구조건을 만족할 수 있는지 실험 결과를 토대로 분석한다.

• 대한임베디드공학회논문지
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• 제10권4호
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• pp.189-198
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• 2015

Most IoT-related approaches have tried to establish the relation by connecting the network between things. The proposed research will present how the pervasive interaction of eco-system formed by touching the objects between humans and things can be recognized on purpose. By collecting and sharing the detected patterns among all kinds of things, we can construct the environment which enables individualized interactions of different objects. To perform the aforementioned, we are going to utilize technical procedures such as event-driven signal processing, pattern matching for signal recognition, and hardware in the loop simulation. We will also aim to implement the prototype of sensor processor based on Arduino MCU, which can be integrated with system using Arduino-Matlab/Simulink hybrid-interoperation environment. In the experiment, we use piezo transducer to detect the vibration or vibrates the surface using acoustic wave, which has specific frequency spectrum and individualized signal shape in terms of time axis. The signal distortion in time and frequency domain is recorded into memory tracer within sensor processor to extract the meaningful pattern by comparing the stored with lookup table(LUT). In this paper, we will contribute the initial prototypes for the acoustic touch processor by using off-the-shelf MCU and the integrated framework based on Matlab/Simulink model to provide the individualization of the touch-sensing for the user on purpose.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}