• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.4
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• pp.251-258
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• 1986

There is much redundancy in image data such as TV signals and many techniques to redice it have been studied. In this paper, Hadamard transform is studied through computer simulation and experimental model. Each element of hadamard matrix is either +1 or -1, and the row vectors are orthogonal to another. Its hardware implementation is the simplest of the usual orthogonal transforms because addition and sulbraction are necessary to calculate transformed signals, while not only addition but multiplication are necessary in digital Fourier transform, etc. Linclon data (64$ imes$64) are simulated using 8th-order and 16th-order Hadamard transform, and 8th-order is implemented to hardware. Theoretical calculation and experimental result of 8th-order show that 2.0 bits/sample are required for good quality.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.87-92
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• 2010

The design of avionic embedded systems requires high-dependability. In this paper, we studied the dependability of the triple modular redundancy (TMR) hardware for highly reliable aviation embedded system. In order to evaluate the dependability of the base ARM processor and the TMR ARM processor, we developed the simulation model of the reduced ARM and TMR ARM processors and performed the simulation fault injection for the analysis of the dependability of the two targets. In the fault injection experiments, we calculated the error recovery rate of the two the processor models. From the experimental results, we could confirm that the reliability of the TMR ARM processor was greater than the single ARM processor by ten times in some cases.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.267-270
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• 2000

In this paper, we consider the simple redundant structures with the function of hardware based active/standby control. The system includes two switch modules. The switch module is connected to a data bus, but only the active switch module has control of the data bus. The standby unit takes over the function of the active unit when the active unit failure or mode command are asserted. And this paper illustrate the high-speed router system and the overall redundant system architecture. The proposed redundant architecture for 80G Router system is verified and implemented with experiment.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.213-215
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• 1987

As a means of improving the reliability of the analog type controller for the thermal power plant, an efficient method is proposed, which is to place the hardware redundancy, i.e. a back-up controller with fault detecting capability. FTCS is implemented by using multi-processors and it is experimentally verified that the back-up controller takes over the role of the original controller, controlling the faulty loop.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• Journal of the Korean Society for Railway
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• v.9 no.6 s.37
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• pp.725-731
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• 2006

Hot Standby sparing system detecting faults by using software, and being tolerant any faults by using Hardware Redundancy is difficult to perform quantitative reliability prediction and to detect real time faults. Therefore, this paper designs Hot Standby sparing system using hardware basis self checking logic in order to overcome this problem. It also performs failure mode analysis of Hot Standby sparing system with designed self checking logic by using FMEA (Failure Mode Effect Analysis), and identifies reliability assessment of the controller designed by quantifying the numbers of failure development by using FTA (Fault Tree Analysis)

• Journal of Power Electronics
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• v.16 no.2
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• pp.522-531
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• 2016

This paper proposes a new NLC (Nearest Level Control) scheme for MMCs (Modular Multilevel Converters), which offers voltage ripple reductions in the DC capacitor of the SM (Sub-Module), the output voltage harmonics, and the switching losses. The feasibility of the proposed NLC was verified through computer simulations. Based on these simulation results, a hardware prototype of a 10kVA, DC-1000V MMC was manufactured in the lab. Experiments were conducted to verify the feasibility of the proposed NLC in an actual hardware environment. The experimental results were consistent with the results obtained from the computer simulations.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.417-433
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• 1997

A real-time operating system has focused primary on techniques to minimize processing time, with a secondary emphasis on system reliability issues. Conversely, fault-tolerant system has concentrated on using recourse and information redundancy to maximize the availability and reliability of the system, with a lesser emphasis on performance. We have developed a fault-tolerant and real-time operations system which support a powerful concurrent runtime environment under the above requirements. In this paper, we present an overview of real-time systems, design and implementation of a duplex architecture using advanced concepts and technologies such as fast " fault detection", "fault isolation" and "fault recovery" Because the duplex architecture has two dentical hardware elements and has several recovery steps and hierarchy to facilitate a fast recovery which must be proceeded by a prompt fault detection and isolation. Thus it makes possible to minimize the overhead of the systems including hardware and software and guarantee the service continuity of he systems.

• Journal of the Korea Society of Computer and Information
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• v.20 no.10
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• pp.1-5
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• 2015

Based on the dual hardware and software with distributed recovery blocks, the centralized type fault tolerant store management system(SMS) was proposed. As a result of trade off study related to mutiplex hardware system design, dual single board computer(SBC) was adapted. To verify redundancy function of the proposed structure, the prototype SMS and weapon simulator were used. The proposed SMS operated normally without being affected by a primary SBC failure. The switching time from primary SBC to shadow SBC was within 200 ms. The reliability of the proposed SMS was predicted and compared with the non fault tolerant SMS, thereby it was proved that the proposed SMS has a higher reliability than the non fault tolerant system within effective range.

• Journal of Multimedia Information System
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• v.5 no.4
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• pp.273-276
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• 2018

In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.