• Investigative Magnetic Resonance Imaging
• /
• v.4 no.1
• /
• pp.20-26
• /
• 2000

Gradient moment nulling techniques require the introduction of an additional gradient on each axis for each order of motion correction to be applied. The additional gradients introduce new constraints on the sequence design and increase the demands on the gradient system. The purpose of this paper is to demonstrate techniques for optimization of gradient echo gradient moment nulling sequences within the constraints of the gradient hardware. Flow compensated pulse sequences were designed and implemented on a clinical magnetic resonance imaging system. The design of the gradient moment nulling sequences requires the solution of a linear system of equations. A Mathematica package was developed that interactively solves the gradient moment nulling problem. The package allows the physicist to specify the desired order of motion compensation and the duration of the gradients in the sequence with different gradient envelopes. The gradient echo sequences with first, second, and third order motion compensation were implemented with minimum echo time. The sequences were optimized to take full advantage of the capabilities of the gradient hardware. The sequences were used to generate images of phantoms and human brains. The optimized sequences were found to have better motion compensation than comparable standard sequences.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.3
• /
• pp.37-44
• /
• 2000

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.

• Design & Manufacturing
• /
• v.12 no.1
• /
• pp.18-25
• /
• 2018

Both injection and injection molding dies have evolved into advanced technology. Product quality is also evolving day after day. Therefore, the conditions of the injection mold and the injection conditions are becoming important. In order to improve the quality of the product, the Hardware part of the mold has developed as an advanced technology, and the Software part has also developed with advanced technology. This study deals with the cooling part, which is part of the hardware. In addition to fluid cooling, which is commonly used in the industry, by using gas cooling identify the phenomena that appear on the surface of the product and the critical point strain of the product to find the optimal cooling. Electronic parts and automobile parts whose surface condition is important, the cooling process is important to such a degree that they are divided with good products and defective products according to the cooling process at the time of injection. By controlling this important cooling and reducing the injection time with additional cooling, the product quality can be increased to the highest production efficiency. In addition, high efficiency can be achieved without additional investment costs. This study was conducted to apply these various advantages in the field.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.9
• /
• pp.37-44
• /
• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Journal of Power Electronics
• /
• v.14 no.4
• /
• pp.733-741
• /
• 2014

The integration of photovoltaic (PV) energy sources into DC grid has gained considerable attention because of its enhanced conversion efficiency with reduced number of power conversion stages. During the integration process, a local control unit is normally included with every power conversion stage of the PV source to accomplish the process of maximum power point tracking. A centralized monitoring and supervisory control unit is required for monitoring, power management, and protection of the entire system. Therefore, we propose a field-programmable gate array (FPGA) based centralized control unit that integrates all local controllers with the centralized monitoring unit. The main focus of this study is on the process of integrating many local control units into a single central unit. In this paper, we present design and optimization procedures for the hardware implementation of FPGA architecture. Furthermore, we propose a transient analysis and control design methodology with consideration of the nonlinear characteristics of the PV source. Hardware experiment results verify the efficiency of the central control unit and controller design.

• Journal of Broadcast Engineering
• /
• v.24 no.6
• /
• pp.1064-1071
• /
• 2019

Multiview stereo matching algorithm is used to reconstruct 3D shape from a set of 2D images. Conventional multiview stereo algorithms have been implemented on high-performance hardware due to the heavy complexity that contains a large number of calculations in each step. However, as the performance of mobile graphics processors has recently increased rapidly, complex computer vision algorithms can now be implemented on mobile devices like a smartphone and an embedded board. In this paper we parallelize an multiview stereo algorithm using OpenCL on mobile GPU and provide various optimization techniques on the embedded hardware with limited resource.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.7
• /
• pp.1480-1483
• /
• 2009

In this paper, the hardware(HW) and software(SW) co-design methodology of H.264/AVC decoder using ARM-Excalibur is proposed. The SoC consists of embedded processor, memory, peripheral device and logic circuits. Recently, the co-design method which designs simultaneously HW and SW part is a new paradigm in SoC design. Because the optimization for partitioning the SoC system is very difficult, the verification must be performed earlier in design flow. We designed the H.264 and AVC Decoder using co-design method. It is shown that, for the proposed co-design method, the performance improvements can be obtained.

• Journal of Information Processing Systems
• /
• v.15 no.2
• /
• pp.374-385
• /
• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• The Journal of the Convergence on Culture Technology
• /
• v.9 no.1
• /
• pp.771-776
• /
• 2023

Scratchpad memory is a software-controlled on-chip memory designed and used to mitigate the disadvantages of existing cache memories. Existing cache memories have TAG-related hardware control logic, so users cannot directly control cache misses, and their sizes are large and energy consumption is relatively high. Scratchpad memory has advantages in terms of size and energy consumption because it eliminates such hardware overhead, but there is a burden on software to manage data. In this study, data management techniques of scratchpad memory were classified and examined, and ways to maximize the advantages were discussed.

• Current Optics and Photonics
• /
• v.7 no.6
• /
• pp.745-754
• /
• 2023

In order to test the recognition ability and accuracy of a target imaging simulator under the irradiation of solar stray light in a laboratory environment, it needs to be fixed on a five-axis turntable during a hardware-in-the-loop simulation test, so the optical system of the simulator should have a long exit pupil distance. This article adopts a secondary imaging method to design a projection optical system suitable for thin-film-transistor liquid crystal displays. The exit pupil distance of the entire optical system is 1,000 mm, and the final optimization results in the 400 nm-850 nm band show that the modulation transfer function (MTF) of the optical system is greater than 0.8 at the cutoff frequency of 72 lp/mm, and the distortion of each field of view of the system is less than 0.04%. Combined with the design results of the optical system, TracePro software was used to model the optical system, and the simulation of the target imaging simulator at the magnitude of -1 to +6 Mv was analyzed and verified. The magnitude error is less than 0.2 Mv, and the irradiance uniformity of the exit pupil surface is greater than 90%, which meets the requirements of the target imaging simulator.