• Journal of Internet Computing and Services
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• v.2 no.4
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• pp.69-81
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• 2001

This paper describes a parallel programming environment to help programmer to write parallel programs. Parallel program must be write according to the character of the various hardware or program. So it is difficult for the programs to write the parallel programmer. In this paper, we propose and implement a parallel programming environment using graph type intermediate representation form, and graph user interface is provided for programmer to get parallel programs easily, This parallel environment supports special functions using graph type intermediate representation form. The special functions involve program editing. data dependence analysis, loop transformation. CFG, PDG, HTG. This parallel environment helps users make parallelism and optimization easy through showing the intermediate code with graph.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.174-177
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• 2016

Wireless network-on-chip (WNoC) can alleviate critical path problem of existing typical NoCs by integrating radio-frequency module on router. In this paper, core-connection-aware genetic algorithm-based core and WIR mapping methodology at small world WNoC is presented. The methodology could optimize the critical path between cores with heavy communication. The 33% of average latency improvement is achieved compared to random mapping methodology.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.29-34
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• 2010

This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.40-44
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• 2010

The timing error detector(TED) employed in the closed loop type timing synchronization scheme for an MQASK all digital receiver suffers from the selfnoise-induced timing jitter. To eliminate the timing jitter a prefilter can be added in front of the TED. The prefilter method, however, degrades the stability and timing acquisition performance due to the loop delay and increases the complexity of the synchronizer. This paper proposes a polyphase filter type resampler approach to optimize the performance and architecture of the synchronizer simultaneously. The proposed scheme uses two resamplers which performs matched filtering and matched prefiltering so that the loop delay is minimized with minimal hardware resources. Simulation results showed an excellent acquisition performance with reduced timing jitter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5654-5668
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• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.4
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• pp.211-221
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• 2012

The development of wireless sensor networks (WSNs) is progressed slowly due to limited resources, but it is in progress to the development of the latest IP-based IP-WSN by the development of hardware and power management technology. IPv6 over Low power WPAN (6LoWPAN) is capable of IPv6-built low-power devices. In these IP-based WSNs, existing IP-based techniques which was impossible in WSNs becomes possible. 6LoWPAN is based on the IEEE 802.15.4 sensor networks and is a IPv6-supported technology. Host-based mobility management scheme in IP-WSNs are not suitable due to the additional signaling, network-based mobility management scheme is more suitable. In this paper, we propose an enhanced PMIPv6-based route optimization scheme which consider multi-6LoWPAN network environments. All SLMA (Sensor Local Mobility Anchor) of the 6LoWPAN domain are connected with the SPIG (Sensor Proxy Internetworking Gateway) and performs distributed mobility control for the 6LoWPAN-based inter-domain operations. All information of SLMA in 6LoWPAN domain is maintained by SMAG (Sensor Mobile Access Gateway), and then is performed the route optimization quickly. The status information of the route optimization from SPIG is stored to SLMA and it is supported without additional signaling.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.3
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• pp.181-192
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• 2022

Active vibration control system(AVCS) for helicopter enables to control the vibration generated from the main rotor and has the superb vibration reduction performance with low weight compared passive vibration reduction device. In this paper, FxLMS algorithm-based vibration control software of the light civil helicopter tansmits the control command calculated using the signals of the tachometer and accelerometers to the circular force generator(CFG) is developed and verified. According to the RTCA DO-178C/DO-331, the vibration control software is developed through the model based design technique, and real-time operation performance is evaluated in PILS(processor in-the loop simulation) and HILS(hardware in-the loop simulation) environments. In particular, the reliability of the software is improved through the LDRA-based verification coverage in the PIL environments. In order to AVCS to light civil helicopter(LCH), the dynamic response characteristic model is obtained through the ground/flight tests. AVCS configuration which exhibits the optimal performance is determined using system optimization analysis and flight test and obtain STC certification.