• Title/Summary/Keyword: hardware optimization

Search Result 210, Processing Time 0.026 seconds

An Efficient ATM Traffic Generator for the Real-Time Production of a Large Class of Complex Traffic Profiles

  • Loukatos Dimitrios;Sarakis Lambros;Kontovasilis Kimon;Mitrou Nikolas
    • Journal of Communications and Networks
    • /
    • v.7 no.1
    • /
    • pp.54-64
    • /
    • 2005
  • This paper presents an advanced architecture for a traffic generator capable of producing ATM traffic streams according to fully general semi-Markovian stochastic models. The architecture employs a basic traffic generator platform and enhances it by adding facilities for 'driving' the cell generation process through high-level specifications. Several kinds of optimization are employed for enhancing the software's speed to match the hardware's potential and for ensuring that traffic streams corresponding to models with a wide range of parameters can be generated efficiently and reliably. The proposed traffic generation procedure is highly modular. Thus, although this paper deals with ATM traffic, the main elements of the architecture can be used equally well for generating traffic loads on other networking technologies, IP-based networks being a notable example.

CRASHWORTHINESS IMPROVEMENT OF VEHICLE-TO-RIGID FIXED BARRIER IN FULL FRONTAL IMPACT USING NOVEL VEHICLE'S FRONT-END STRUCTURES

  • ELMARAKBI A. M.;ZU J. W.
    • International Journal of Automotive Technology
    • /
    • v.6 no.5
    • /
    • pp.491-499
    • /
    • 2005
  • There are different types of vehicle impacts recorded every year, resulting in many injuries and fatalities. The severity of these impacts depends on the aggressivety and incompatibility of vehicle-to-roadside hardware impacts. The aim of this paper is to investigate and to enhance crashworthiness in the case of full barrier impact using a new idea of crash improvement. Two different types of smart structures have been proposed to support the function of the existing vehicle. The work carried out in this paper includes developing and analyzing mathematical models of vehicle-to-barrier impact for the two types of smart structures. It is proven from analytical analysis that the mathematical models can be used in an effective way to give a quick insight of real life crashes. Moreover, it is shown that these models are valid and flexible, and can be useful in optimization studies.

Noninvasive Hematocrit Monitoring Based on Parameter-optimization of a LED Finger Probe

  • Yoon, Gil-Won;Jeon, Kye-Jin
    • Journal of the Optical Society of Korea
    • /
    • v.9 no.3
    • /
    • pp.107-110
    • /
    • 2005
  • An optical method of measuring hematocrit noninvasively is presented. An LED Light with multiple wavelengths was irradiated on fingernail and transmitted light from the finger was measured to predict hematocrit. A finger probe contained an LED array and detector. Our previous experience showed that prediction accuracy was sensitive to reliability of the finger probe hardware and we optimized the finger probe parameters such as the internal color, detector area and the emission area of a light source based on Design of Experiment. Using the optimized finger probe, we developed a hematocrit monitoring system and tested with 549 persons. For the calibration model with 368 persons, a regression coefficient of 0.74 and a standard deviation of 3.67 and the mean percent error of $8\%$ were obtained. Hematocrits for 181 persons were predicted. We achieved a mean percent error of $8.2\%$ where the regression coefficient was 0.68 and the standard deviation was 3.69.

The Hardware Design and Implementation of the Support Vector Machines (SVM(Support Vector Machines)의 하드웨어 설계 및 구현)

  • 진종렬;김동성;박종서
    • Proceedings of the Korean Information Science Society Conference
    • /
    • 2004.04b
    • /
    • pp.592-594
    • /
    • 2004
  • 본 논문에서는 SVM의 효과적인 학습 알고리즘인 SMO(Sequential Minimal Optimization)를 하드웨어적으로 설계하고 구현하는 방법을 제시한다. SVM은 Vapnik에 의한 제안된 기계학습 방법으로 음성인식, 문자인식, BT, 보안 등 다양한 응용분야에서 기존의 신경망보다 우수한 성능을 나타내었다. 그러나 SVM은 계산량이 많아 연산속도가 느려지는 단점을 가진다. 이를 개선하기 위해 본 논문에서는 SVM의 학습 알고리즘인 SMO의 핵심인 지수함수와 실수 연산기를 VHDL로 설계하고 Mentor의 ModelSim을 이용하여 시뮬레이션하고 Synopsys의 Design Analyzer를 이용하여 합성하였다. 구현된 칩은 시뮬레이션 결과 약 50MHz의 속도로 동작하며, 이는 소프트웨어적으로 구현된 SMO보다 약 10~20배 빠른 성능을 나타내었다.

  • PDF

Topology Design Optimization for Improving Fail-over Performance in Wired Mesh Network (유선 메시 구조에서의 절체 성능 향상을 위한 네트워크 설계 기법)

  • Hwang, Jongsu;Jang, Eunjeong;Lee, Wonoh;Kim, Jonghyeok;Kim, Heearn
    • IEMEK Journal of Embedded Systems and Applications
    • /
    • v.14 no.4
    • /
    • pp.165-175
    • /
    • 2019
  • Networks use relatively slow heartbeat mechanisms, usually in routing protocols, to detect failures when there is no hardware signaling to help out. The time to detect failures available in the existing protocols is no better than a second, which is far too long for some applications and represents a great deal of lost data at 10 Gigabit rates. We compare the convergence time of routing protocol applying Bidirectional Forwarding Detection (BFD) protocol in wired mesh network topology. This paper suggests the combinations of protocols improving fail-over performance. Through the performance analysis, we contribute to reduce convergence time when system is fail-over.

A Study on Optimal Design of Capacitance for Active Power Decoupling Circuits (능동 전력 디커플링 회로의 커패시턴스 최적 설계에 관한 연구)

  • Baek, Ki-Ho;Park, Sung-Min;Chung, Gyo-Bum
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.24 no.3
    • /
    • pp.181-190
    • /
    • 2019
  • Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

Optimization of Microgrid Energy Network and Test on HILS System (마이크로 에너지 네트워크 최적화 및 HILS 기반의 테스트)

  • Lee, Ji-Hye;Yoo, Hyeong-Jun;Kim, Nam-Dae;Jeon, Chang-Jo;Kim, Hak-Man;Im, Yong Hoon;Lee, Jae Yong
    • Annual Conference of KIPS
    • /
    • 2013.05a
    • /
    • pp.416-417
    • /
    • 2013
  • 마이크로 에너지 네트워크란 건물군 내 에너지 수요를 최소한의 비용으로 충족시키기 위하여 다양한 에너지원으로 구성되어 있는 네트워크이다. 본 논문에서는 마이크로 에너지 네트워크의 최적 운용을 위한 마이크로 에너지 네트워크 EMS (Energy Management System)의 핵심 기능을 구현하고, 이를 HILS (Hardware-in-the-Loop Simulation) 시스템을 이용하여 추후 실제 마이크로 에너지 네트워크에 대한 적용 가능성을 검토하고자 한다.

Parallel Implementation of Scrypt: A Study on GPU Acceleration for Password-Based Key Derivation Function

  • SeongJun Choi;DongCheon Kim;Seog Chung Seo
    • Journal of information and communication convergence engineering
    • /
    • v.22 no.2
    • /
    • pp.98-108
    • /
    • 2024
  • Scrypt is a password-based key derivation function proposed by Colin Percival in 2009 that has a memory-hard structure. Scrypt has been intentionally designed with a memory-intensive structure to make password cracking using ASICs, GPUs, and similar hardware more difficult. However, in this study, we thoroughly analyzed the operation of Scrypt and proposed strategies to maximize computational parallelism in GPU environments. Through these optimizations, we achieved an outstanding performance improvement of 8284.4% compared with traditional CPU-based Scrypt computations. Moreover, the GPU-optimized implementation presented in this paper outperforms the simple GPU-based Scrypt processing by a significant margin, providing a performance improvement of 204.84% in the RTX3090. These results demonstrate the effectiveness of our proposed approach in harnessing the computational power of GPUs and achieving remarkable performance gains in Scrypt calculations. Our proposed implementation is the first GPU implementation of Scrypt, demonstrating the ability to efficiently crack Scrypt.

Understanding the Relationship between Particle Size, Performance and Pressure (입자 크기, 성능 및 압력 간의 관계 이해)

  • Matt James
    • FOCUS: LIFE SCIENCE
    • /
    • no.1
    • /
    • pp.7.1-7.4
    • /
    • 2024
  • The document "Understanding the Relationship Between Particle Size, Performance, and Pressure" explores the impact of particle size on chromatographic performance and system pressure. The study highlights how smaller particles can improve separation efficiency by providing higher resolution and faster analysis times. However, this comes at the cost of increased backpressure, which can challenge the system's hardware and require higher operating pressures. The document discusses the balance needed between particle size, column dimensions, and system pressure to optimize performance without exceeding the pressure limits of chromatographic systems. It outlines the advantages of using superficially porous particles (SPPs) over fully porous particles (FPPs) in achieving high efficiency with lower backpressure. The study also emphasizes the importance of selecting appropriate column dimensions and flow rates to manage system pressure while maintaining optimal performance. In conclusion, understanding the interplay between particle size, performance, and pressure is crucial for optimizing chromatographic separations, ensuring system longevity, and achieving high-quality analytical results.

  • PDF

Performance Optimization Strategies for Fully Utilizing Apache Spark (아파치 스파크 활용 극대화를 위한 성능 최적화 기법)

  • Myung, Rohyoung;Yu, Heonchang;Choi, Sukyong
    • KIPS Transactions on Computer and Communication Systems
    • /
    • v.7 no.1
    • /
    • pp.9-18
    • /
    • 2018
  • Enhancing performance of big data analytics in distributed environment has been issued because most of the big data related applications such as machine learning techniques and streaming services generally utilize distributed computing frameworks. Thus, optimizing performance of those applications at Spark has been actively researched. Since optimizing performance of the applications at distributed environment is challenging because it not only needs optimizing the applications themselves but also requires tuning of the distributed system configuration parameters. Although prior researches made a huge effort to improve execution performance, most of them only focused on one of three performance optimization aspect: application design, system tuning, hardware utilization. Thus, they couldn't handle an orchestration of those aspects. In this paper, we deeply analyze and model the application processing procedure of the Spark. Through the analyzed results, we propose performance optimization schemes for each step of the procedure: inner stage and outer stage. We also propose appropriate partitioning mechanism by analyzing relationship between partitioning parallelism and performance of the applications. We applied those three performance optimization schemes to WordCount, Pagerank, and Kmeans which are basic big data analytics and found nearly 50% performance improvement when all of those schemes are applied.