• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1982.10a
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• pp.56-58
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• 1982

New acquisition method in synchronization of the PN-modulated spread spectrum system is presented. Microprocessor is adopted for its flexibility and the hardware complexity when not used.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.77-82
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• 2015

Recently, multi-user massive MIMO (MU-Massive MIMO) network has attracted a lot of attention as a technology to accommodate explosively increasing mobile data traffic. However, the MU-Massive MIMO network causes a tremendous hardware complexity in a base station and computational complexity to select optimal set of users. In this paper, we thus propose a simple algorithm for selecting antennas and users while reducing the hardware and computational complexities simultaneously. The proposed scheme has a computational complexity of $O((N-S_a+1){\times}min(S_a,K))$, which is significantly reduced compared to the complexity of optimal scheme based on Brute-Force searching, $$O\left({_N}C_S_a\sum_{i=1}^{min(S_a,K)}_KC_i\right)$$, where N, $S_a$, and K denote the number of total transmit antennas, the number of selected antennas, and the number of all users, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.27-36
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• 2005

This paper presents an area-efficient architecture to implement the high-speed Reed-Solomon(RS) decoder, which is used in a variety of communication systems such as wireless and very high-speed optical communications. We present the new pipelined-recursive Modified Euclidean(PrME) architecture to achieve high-throughput rate and reducing hardware-complexity using folding technique. The proposed pipelined recursive architecture can reduce the hardware complexity about 80$\%$ compared to the conventional systolic-array and fully-parallel architecture. The proposed RS decoder has been designed and implemented with the 0.13um CMOS technology in a supply voltage of 1.2 V. The result show that total number of gate is 393 K and it has a data processing rate of S Gbits/s at clock frequency of 625 MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.96-103
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• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• Journal of the Korea Society of Computer and Information
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• v.19 no.1
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• pp.77-84
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• 2014

In this paper, we propose the hierarchical network synchronization scheme that is backward compatible for the existing commercial system, efficient for total system performance, and whose hardware modification is minimized. This system performance is, the relationship among bandwidth efficiency, complexity and MODEM performance, and superiority of network system applicability. The proposed structure can remedy the high hardware complexity and the lower accuracy of network sychronization that the existing satellite communication terminal system in the star network based on TDM/MF-TDMA of DVB-S2/RCS standards has. Besides, It has high efficiency in view of cost and system performance if the system designed for satellite broadcast requires system upgrade. In the body section, its hardware complexity and system performance of the proposed algorithm is analysed theoretically and treated with the related parameters(symbol rate, spreading factor, etc.) and the BER performance of control channel through the computer simulation for its verification that it can be applied for communications system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.10
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• pp.53-59
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• 2011

In recent years, mobile communication service is used extensively as a larger service area for the maintenance of quality of service required by the expansion of service areas and As the ever-increasing role in relays, and the location is relatively easy to install and less constrained costs, operating cost savings in terms of ICS(Interference Cancellation System) repeaters are required. However, an adaptive algorithm that is applied when updating the filter due to the increase in volume of operations increase the complexity of hardware implementation is fraught with many difficulties. In this paper, if there is a path that feedback. ICS repeater utilizing baseband signal processing for the removal of interfering signals from the feedback operation, significantly reducing the amount of reducing hardware complexity Complex Singed Signed LMS adaption algorithm is proposed. Proposed algorithm for evaluating the performance of Static channel WCDMA signal environment for the ICS, the results of the simulation algorithm, convergence speed and better performance in therms of convergence errors that are required through the implementation of the operation greatly reduces the amount of hardware complexity able to reduce the effect was visible.

• Journal of IKEEE
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• v.19 no.1
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• pp.45-51
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• 2015

Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.