• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.3
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• pp.57-63
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• 2005

Kim and Fenn et al. proposed two modular AB multipliers based on LFSR(Linear Feedback Shift Register) architecture. These multipliers use AOP, which has all coefficients with '1', as an irreducible polynomial. Thereby, they have good hardware complexity compared to the previous architectures. This paper proposes a modular $AB^2$ multiplier based on LFSR architecture and a modular exponentiation architecture to improve the hardware complexity of the Kim's. Our multiplier also use the AOP as an irreducible polynomial as the Kim architecture. Simulation result shows that our multiplier reduces the hardware complexity about $50\%$ in the perspective of XOR and AND gates compared to the Kim's. The architecture could be used as a basic block to implement public-key cryptosystems.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.10
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• pp.11-20
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• 2002

This paper proposes a hardware/software codesign of the MLSE equalizer for GSM.GPRS systems. We analyze algorithms of the MLSE equalizer which consists of a channel estimator using the correlation method and the Viterbi processor. We estimate the computational complexity requirement based on the simulation of TI TMS320C5x DSP. We also estimate the gate count from the results of logic synthesis using the samsung 0.5㎛ standard cell library (STD80). Based on the results of the complexity estimation and gate count, we propose the efficient software/hardware codesign of the MLSE equalizer based on the results of the complexity estimation and gate count.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1113-1116
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• 1998

This paper presents an efficient hardware architecture of demodulating fingers to demodulate the multi-path propagating signals in MC-CDMA Mobile System. We design a new architecture of demodulating fingers which share the single arithmetic unit to reduce the hardware complexity. This arithmetic unit performs MAC(Multiplication and Accumulation) operations of all demodulating fingers. The proposed architecture is suitable for Is-95 based CDMA PCS system. Three demodulating fingers for MC-CDMA which demodulate 7 channels contain about 42K logic gates. Our proposed system is shown to be very useful for Multi-Code CDMA system in which several channels are demodulated simultaneously.

• International Journal of Contents
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• v.7 no.1
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.3
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• pp.121-125
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• 2014

A hardware implementation of Hilbert transform is indespensible element in DSP system, but it suffers form a high complexity of system level hardware resulted in a large amount of the used gate. In this paper, we implemented the Hilbert transformer using MAG algorithm that reduces the complexity of hardware.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.4 no.1
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• pp.11-15
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• 1986

In the new futre, computer system designers are expeted to bring more computer power to more people than is currently feasible. At the same time. it is reasonable for the computer system desigers to expect the computer architects to prodce hardware structures incorporating system algorithms of greated complexity so that more of the general instructions go to serving the users. In the past, the architect has delivered more computing to the user by constructing bigger and faster central processors, possibly connecting two or three CPUs together This approach has its limitations, in cost, complexity and reliability. In this paper, we first briefly discuss the hardware environment on which Hydra was implemented, then discuss the philosophy on which the system is based, and finally exhibit the protection mechanism.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1793-1802
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• 2000

In this paper we propose an efficient implementation technique for cyclic extension in VDSL(Very High bit-rate Digital Subscriber Line) systems using Zipper duplexing and analyze its performances under typical telephone channel environments. In Zipper-based VDSL systems each DTM(discrete-multitone) block is appended by both cyclic prefix(CP) and cyclic suffix(CS). The CP is inserte to prevent both intersymbol interference (ISI) and iterchannel interference (ICI) while the CS is appended to ensure orthogonality between the upstream and downstream carriers thus preventing near-end crosstalk (NEXT). However in order to implement the CP in the transmitter side of the VDSL system an additional hardware is required to append the latter part of each DMT symbol to the beginning of the DMT symbol. In this paper we propose a VDSL system with Zipper duplexing using only CS to reduce hardware complexity (memory and processing delay) required for implementation of CP. It is shown by computer simulation that the proposed approach has the same capacity under typical channel environments as the previous Zipper-based VDSL system using both CP and CS. even with a significantly lower hardware complexity.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.20-25
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• 2016

This study addresses a low complexity and lossless frame memory compression algorithm based on block-buffer structure for efficient high resolution video processing. Our study utilizes the block-based MHT (modified Hadamard transform) for spatial decorrelation and AGR (adaptive Golomb-Rice) coding as an entropy encoding stage to achieve lossless image compression with low complexity and efficient hardware implementation. The MHT contains only adders and 1-bit shift operators. As a result of AGR not requiring additional memory space and memory access operations, AGR is effective for low complexity development. Comprehensive experiments and computational complexity analysis demonstrate that the proposed algorithm accomplishes superior compression performance relative to existing methods, and can be applied to hardware devices without image quality degradation as well as negligible modification of the existing codec structure. Moreover, the proposed method does not require the memory access operation, and thus it can reduce costs for hardware implementation and can be useful for processing high resolution video over Full HD.