• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.509-513
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• 2004

An area of research called evolvable hardware (EHW) has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. This paper gives an introduction to the field. It continues by including classifying the EHW and the applications of the area.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.129-140
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• 1994

In this paper we investigate the hardware implementation of block matching algorithms (BMAs) for moving sequences. Using systolic arrays we propose a hardware architecture of a two-stage BMA using integral projections which reduces greatly computational complexity with its performance comparable to that of the full search (FS). Proposed hardware architecture is faster than hardware architecture of the FS by 2~15 times. For realization of the FS and two stage BMA modeling and simulation results using SPW and VHDL are also shown.

• The Mathematical Education
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• v.47 no.4
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• pp.505-517
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• 2008

This paper studies on the necessity of mathematics/statistics in software and hardware fields. First, this research analyzes the contents of mathematics/statistics among subjects in software and hardware fields. Secondly, this research explores the relationship and connectivity between mathematics/statistics and major tracks of software and hardware fields. This connectivity between mathematics/statistics and majors in software and hardware fields would certainly contribute to creating pragmatic and professional knowledge.

• Journal of KIISE:Software and Applications
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• v.31 no.10
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• pp.1364-1373
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• 2004

Recently Evolvable Hardware (EHW) is widely studied to design effective hardware circuits that can reconfigure themselves according to the environment. However, it is still difficult to apply for complicated circuits because the search space increases exponentially as the complexity of hardware increases. To remedy this problem, this paper proposes a method to evolve complex hardware with a modular approach. The comparative experiments of some digital circuits with the conventional evolutionary approach indicate that the proposed method yields from 50 times to 1,000 times faster evolution and more optimized hardware.

• Journal of the Korea Safety Management & Science
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• v.15 no.2
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• pp.63-69
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• 2013

The purposes of this study are to survey stereotypes of control-display relationships for seven principal controls in passenger cars using the paper-pencil and hardware tests, and to examine stereotype strength of the paper-pencil test through comparing the stereotypes for the controls derived by the two methods. Ninety two and 60 college-aged students participated in the paper-pencil test and the real car simulation of the hardware test, respectively. There are dominant motion-directions for all controls in the paper-pencil test, while in the hardware test, there are dominant motion-directions for six controls including head light, high beam, door window, ignition key, door key and door lock controls. The stereotypes of motion-directions for six controls obtained by the paper-pencil test were the same as or similar to those by the hardware test. It was inferred from this that the congruence of the stereotypes by the two methods might be attributed to two simple motion-direction principles of 'clockwise for increase' and 'upward for increase.' Although it is known that the hardware test would be best for obtaining accurate stereotypes between controls and displays, this study implies that if the paper-pencil test is well designed, the paper-pencil test can produce the same results as the hardware test at low cost and without consuming time.

• Journal of IKEEE
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• v.25 no.1
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• pp.10-14
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• 2021

This paper presents a hardware that improves the complexity of the CIE1931 color coordinate algorithm operation. The conventional algorithm has disadvantage of growing hardware due to 4-Split Multiply operations used to calculate large bits in the computation process. But the proposed algorithm pre-calculates the defined R2X, X2R Matrix operations of the conventional algorithm and makes them a matrix. By applying the matrix to the images and improving the color, it is possible to reduce the amount of computation and hardware size. By comparing the results of Xilinx synthesis of hardware designed with Verilog, we can check the performance for real-time processing in 4K environments with reduced hardware resources. Furthermore, this paper validates the hardware mount behavior by presenting the execution results of the FPGA board.

• ETRI Journal
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• v.45 no.2
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• pp.346-357
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• 2023

Hardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off-the-shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware-based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min-entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high-entropy requirements, such as cryptographic key generation for IoT devices.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.309-311
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• 2005

In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.

• Journal of the Korea Society of Computer and Information
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• v.22 no.8
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• pp.47-53
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• 2017

In this paper, we present open hardware platforms for Internet of Things (IoTs) emphasizing their strengths and weaknesses. We introduce six representative platforms, Raspberry PI, Arduino, Garileo, Edison, Beagle board and Artik. We define important performance issues for open hardware platforms for IoTs and analyze recent platforms according to the performance issues. We present recent research project using open hardware platforms introduced in this paper. We believe that this paper provide wise view and necessary information for open hardware platforms for Internet of Things (IoT).