• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• 한국가시화정보학회:학술대회논문집
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• 2004.04a
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• pp.57-63
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• 2004

최근 일반 범용 PC 에 장착되고 있는 ATI 나 NVIDIA 등의 그래픽스 가속기의 성능은 수년전과 비교할 때 비교가 안 될 정도의 빠른 속도를 자랑하고 있다. 이러한 속도 향상과 함께 급격하게 일어나고 있는 변화 중의 하나는 바로 기존의 고정된 기능의 그래픽스 파이프라인(fixed-function graphics pipeline)과는 달리 프로그래머가 가속기의 기능을 자유자재로 프로그래밍할 수 있도록 해주는 프로그래밍이 가능한 파이프라인(programmable graphics pipeline)의 출현이라 할 수 있다. 이러한 가속기에 장착되고 있는 GPU (Graphics Processing Unit)는 간단한 형태의 SIMD 프로세서라 할 수 있는데, 특히 GPU 의 한 부분인 픽셀 쉐이더는 그 처리 속도가 매우 높기 때문에 이를 통하여 기존의 수치 알고리즘을 병렬화 하려는 시도가 활발히 일어나고 있다. 본 강연에서는 다양한 수치 계산을 그래픽스 가속기를 사용하여 해결하려는 시도에 대하여 간단히 살펴본다.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• Journal of IKEEE
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• v.14 no.2
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• pp.76-81
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• 2010

The need for dedicated hardware continue to decrease as the mobile CPU's performance increases. But, there is a limit to a mobile CPU's performance. GP-GPU(General-Purpose computing on Graphics Processing Units) can improve performance without adding other dedicated hardware. This paper presents the implementation of Inverse Quantization, Inverse DCT and Color Space Conversion module in H.264/AVC decoder using GP-GPU for a mobile environments. The proposed architecture improves approximately 40% of performance when it use all the features.

• Proceedings of the Korea Contents Association Conference
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• 2008.05a
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• pp.131-134
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• 2008

Most games based on PCs or consoles at present show vivid special effects and brilliance sceneries. However, the other games running on mobiles and portable devices can not show magnificent scenes because of low hardware specifications such as slow CPU, old graphics card and battery capacity. These games relatively prefer light and casual contents that do not need tremendous calculation. It is very important to keep minimum of game graphics quality in those games. Thus this research presents that the new possibility of variable indexed color palettes to overcome the low hardware capacities.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.397-404
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• 2013

This paper propose the hardware architecture of face detection hardware system using the AdaBoost algorithm. The proposed structure of face detection hardware system is possible to work in 30frame per second and in real time. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data by Matlab, and finally detected the face using this data. This paper describes the face detection hardware structure composed of image scaler, integral image extraction, face comparing, memory interface, data grouper and detected result display. The proposed circuit is so designed to process one point in one cycle that the prosed design can process full HD($1920{\times}1080$) image at 70MHz, which is approximate $2316087{\times}30$ cycle. Furthermore, This paper use the reducing the word length by Overflow to reduce memory size. and the proposed structure for face detection has been designed using Verilog HDL and modified in Mentor Graphics Modelsim. The proposed structure has been work on 45MHz operating frequency and use 74,757 LUT in FPGA Xilinx Virtex-5 XC5LX330.

• Journal of the Korea Computer Graphics Society
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• v.23 no.3
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• pp.55-64
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• 2017

In this paper, a novel soft shadow method is suggested to support realistic shadows in mobile ray tracing. In ray tracing, soft shadow is generally generated by sampling a shadow ray. As this sampling method increases the number of rays to be processed, it has undermined the performance. We designed the proposed soft shadow processing method and hardware architecture to overcome this problem through selective shadow generation and triangle address caching for minimizing the performance degradation caused by sampling. The proposed hardware architecture can be integrated into a mobile ray-tracing hardware and was evaluated in terms of its performance on the FPGA. Based on the results, the rendering performance about 4, 8, and 16 samples were improved, respectively, by 40%, 50%, and 56% on average compared to the previous method, and it was found that the real-time soft shadow processing is feasible with the proposed hardware architecture.

• Journal of Korea Multimedia Society
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• v.10 no.9
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• pp.1209-1219
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• 2007

It is difficult to run 3D graphics based application on the embedded system with hardware constraints. Therefore, such a system must have a systematic infrastructure which can process various operations with respect to 3D graphics through any graphic acceleration module. In this paper, we present a method to implement 3D graphics acceleration device driver on Tiny X platform which provide an open source graphics windowing environment. The proposed method is to initialize the driver step by step so that the direct rendering infrastructure can use it properly. Moreover, we evaluated overall 3D graphics performance of an implemented driver through a simple but effective benchmark program.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.337-340
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• 2009

Since a hardware accelerator for 3D graphics processing GPU(Graphics Processing Unit)'s performance has been improving constantly. This is the efficient way was introduced for complex graphics application, but it is rarely used to utilize 100% resources on GPU. GP-GPU(general-purpose GPU), including operations on the GPU and supporting common operations can be handled by the processor, is noted by depending on the distribution of resources that can be effectively controlled. In this paper, the simulator was implemented that supports virtual environment of GP-GPU and available for program design and debugging. Through this, the co-design development environment support simultaneous design fast and reliable verification that are available to build the interface of three-dimensional graphics display.

• Journal of the Korea Computer Graphics Society
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• v.23 no.3
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• pp.123-133
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• 2017

Cache performance is an important factor in hardware system. We proceed with a cache simulation to analyze the cache performance suitable for sound rendering. In addition, we introduce hardware models based on ray tracing used in geometric method and studies to improve cache performance. Cache simulation is performed on various conditions for cache size, way and block. Various simulations can be found to influence the cache hit rate. We compare cache simulation results with actual hardware performance to analyze cache performance suitable for sound rendering.