• 한국정보통신학회논문지
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• 제17권8호
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• pp.1891-1898
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• 2013

3차원 그래픽 API인 OpenGL과 Direct3D를 효율적으로 처리하기 위해 sine, cosine, 역수, 역제곱근, 지수 및 로그 연산을 처리하는 부동소수점 연산회로를 설계하였다. 고속 연산과 2 ulp 보다 작은 오차를 만족시키기 위해 2차 최대최소 근사 방식과 테이블 룩업 방식을 사용하였다. 설계된 회로는 65nm CMOS 표준 셀 조건에서 2.3-ns의 최대 지연시간을 갖고 있으며, 약 23,300 게이트로 구성된다. 최대 400 MFLOPS의 연산 성능과 높은 정밀도로, 설계한 연산회로는 3차원 모바일 그래픽 분야에 효율적으로 적용 가능하다.

• 한국멀티미디어학회논문지
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• 제23권2호
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• pp.317-327
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• 2020

R&D(Research and Development) efficiency analysis is a very important issue in academia and industry. Although many studies have been conducted to analyze R&D(Research and Development) efficiency since the past, studies that analyzed R&D(Research and Development) efficiency considering both patentability and patent quality efficiency according to the financial performance of a company do not seem to have been actively conducted. In this study, measuring the patent application and patent quality efficiency according to financial performance, patent quality efficiency according to patent application were applied to corporate groups related to artificial intelligence hardware technology defined as GPU(Graphics Processing Unit), FPGA(Field Programmable Gate Array), ASIC(Application Specific Integrated Circuit) and Neuromorphic. We analyze the efficiency empirically and use Data Envelopment Analysis as a measure of efficiency. This study examines which companies group has high R&D(Research and Development) efficiency about artificial intelligence hardware technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.593-596
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• 2004

This paper presents a low power design of the embedded 3D graphics rendering processor with the double span processing stage. The increase of hardware complexity by using the double span processing stage is ignorable. And the performance is equal to the rendering processor with the single span processing stage. It reduces the power consumption by using different clock frequencies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.715-718
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• 2005

Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

• ETRI Journal
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• 제33권1호
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• pp.89-99
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• 2011

We construct surfaces with darts, creases, and corners by blending different types of local geometries. We also render these surfaces efficiently using programmable graphics hardware. Points on the blending surface are evaluated using simplified computation which can easily be performed on a graphics processing unit. Results show an eighteen-fold to twenty-fold increase in rendering speed over a CPU version. We also demonstrate how these surfaces can be trimmed using textures.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.761-762
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• 2008

This paper presents a hardware accelerator for accelerating vector graphics applications based on the OpenVG standard. Since our design mainly targets embedded applications, we focus on efficient uses of limited resources, especially the memory bandwidth. The designed accelerator can process the images of $640{\times}240$ pixels with moderate complexity at the rate of 30 frames per second.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2006년도 한국컴퓨터종합학술대회 논문집 Vol.33 No.1 (A)
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• pp.196-198
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• 2006

Shader architecture is one of the fastest growing fields in the ever advancing 3D graphics, and massive amounts of Ideas and technologies are being introduced to the market continuously. In this paper, we present a flexible cycle-accurate simulation environment to accelerate and alleviate the process of developing and verifying these ideas and technologies. Combination of 3D graphics API and hardware simulator allows OpenGL applications to be emulated off-the-shelf for a given shader micro-architecture. Easily modified parameters allow the simulation environment to be tailored to specific demands or requirements.

• 한국컴퓨터정보학회논문지
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• 제21권2호
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• pp.9-16
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• 2016

Recently, many research groups have focused on GPGPUs in order to improve the performance of computing systems. GPGPUs can execute general-purpose applications as well as graphics applications by using parallel GPU hardware resources. GPGPUs can process thousands of threads based on warp scheduling and CTA scheduling. In this paper, we utilize the traditional CTA scheduler to assign a various number of CTAs to SMs. According to our simulation results, increasing the number of CTAs assigned to the SM statically does not improve the performance. To solve the problem in traditional CTA scheduling schemes, we propose a new IPC-based dynamic CTA scheduling scheme. Compared to traditional CTA scheduling schemes, the proposed dynamic CTA scheduling scheme can increase the GPU performance by up to 13.1%.

• 한국컴퓨터그래픽스학회논문지
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• 제11권1호
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• pp.40-49
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• 2005

Several optimization techniques have been proposed for volume ray casting, but these cannot achieve real-time frame rates. In addition, it is difficult to apply them to some applications that require perspective projection. Recently, hardware-based methods using 3D texture mapping are being used for real-time volume rendering. Although rendering speed approaches real time, the larger volumes require more swapping of volume bricks for the limited texture memory. Also, image quality deteriorates compared with that of conventional volume ray casting. In this paper, we propose a data structure for real-time volume ray casting named PERM (Precomputed dEnsity and gRadient Map). The PERM stores interpolated density and gradient vector for quantized cells. Since the information requiring time-consuming computations is stored in the PERM, our method can ensure interactive frame rates on a consumer PC platform. Our method normally produces high-quality images because it is based on conventional volume ray casting.

• 한국HCI학회:학술대회논문집
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• 한국HCI학회 2007년도 학술대회 3부
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• pp.322-325
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• 2007

Graphics processing unit (GPU) is used for a faster artificial neural network. It is used to implement the matrix multiplication of a neural network to enhance the time performance of a text detection system. Preliminary results produced a 20-fold performance enhancement using an ATI RADEON 9700 PRO board. The parallelism of a GPU is fully utilized by accumulating a lot of input feature vectors and weight vectors, then converting the many inner-product operations into one matrix operation. Further research areas include benchmarking the performance with various hardware and GPU-aware learning algorithms. (c) 2004 Pattern Recognition Society. Published by Elsevier Ltd. All rights reserved.