• Journal of the Korean Association of Geographic Information Studies
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• v.26 no.3
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• pp.12-36
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• 2023

Graph databases, which store different types of data and their relationships modeled as a graph, can be effective in managing and analyzing real estate spatial data linked by complex relationships. However, they are not widely used due to the limited spatial functionalities of graph databases. In this study, we propose a uniform grid-based real estate spatial data management approach using a graph database to respond to various real estate-related spatial questions. By analyzing the real estate community to identify relevant data and utilizing national point numbers as unit grids, we construct a graph schema that linking diverse real estate data, and create a test database. After building a test database, we tested basic topological relationships and spatial functions using the Jackpine benchmark, and further conducted query tests based on various scenarios to verify the appropriateness of the proposed method. The results show that the proposed method successfully executed 25 out of 29 spatial topological relationships and spatial functions, and achieved about 97% accuracy for the 25 functions and 15 scenarios. The significance of this study lies in proposing an efficient data integration method that can respond to real estate-related spatial questions, considering the limited spatial operation capabilities of graph databases. However, there are limitations such as the creation of incorrect spatial topological relationships due to the use of grid-based indexes and inefficiency of queries due to list comparisons, which need to be improved in follow-up studies.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.47-55
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• 1999

In this paper, a new function hazard elimination algorithm is proposed for asynchronous circuit synthesis. In previous approach, function hazard is eliminated by using state graph which is obtained from the state assignment on STG(signal transition graph) representing transition relationship among signals. These algorithms can use conventional hazard removal and synthesis method applied in synchronous system, but it has much computational complexity and takes much time to handle the state graph. Although some hazard elimination algorithm from STG were proposed, it could not reduce the area overhead due to the addition of new signals. The proposed algorithm eliminate function hazard directly on STG and also control the number of minterms and product-term of added signal in order to minimize the area overhead. Experimental results on benchmark data shows that overall circuit area after hazard elimination is decreased about 15% on the average than that of previous method.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.4
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• pp.1712-1731
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• 2016

In this paper, we propose a novel saliency detection framework via multiple random walks (MRW) which simulate multiple agents on a graph simultaneously. In the MRW system, two agents, which represent the seeds of background and foreground, traverse the graph according to a transition matrix, and interact with each other to achieve a state of equilibrium. The proposed algorithm is divided into three steps. First, an initial segmentation is performed to partition an input image into homogeneous regions (i.e., superpixels) for saliency computation. Based on the regions of image, we construct a graph that the nodes correspond to the superpixels in the image, and the edges between neighboring nodes represent the similarities of the corresponding superpixels. Second, to generate the seeds of background, we first filter out one of the four boundaries that most unlikely belong to the background. The superpixels on each of the three remaining sides of the image will be labeled as the seeds of background. To generate the seeds of foreground, we utilize the center prior that foreground objects tend to appear near the image center. In last step, the seeds of foreground and background are treated as two different agents in multiple random walkers to complete the process of salient object detection. Experimental results on three benchmark databases demonstrate the proposed method performs well when it against the state-of-the-art methods in terms of accuracy and robustness.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.212-215
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• 2002

In this paper, we present an intermediate representation CDFG(Control Data Flow Graph) and an efficient scheduling technique for low power circuit design. The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, iterative rescheduling process are performed in a minimum bound estimation, starting with the as soon as possible as scheduling result, so as to reduce the power consumption in low power design. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

• Korean Management Science Review
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• v.26 no.1
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• pp.65-76
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• 2009

The undirected Steiner tree problem in graphs is known to be NP-hard. The objective of this problem is to find a shortest tree containing a subset of nodes, called terminal nodes. This paper proposes a method based on a two-step procedure to solve this problem efficiently. In the first step. graph reduction rules eliminate useless nodes and edges which do not contribute to make an optimal solution. In the second step, a max-min ant colony optimization combined with Prim's algorithm is developed to solve the reduced problem. The proposed algorithm is tested in the sets of standard test problems. The results show that the algorithm efficiently presents very correct solutions to the benchmark problems.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.79-86
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• 2002

This paper presents a low power scheduling and allocation algorithm for multiple supply voltage. The proposed supply voltage scheduling algorithm determines the control step to execute a possible the operation experimentally using another supply voltage level. Also, the switching activity using component library. and the supply voltage allocation method uses the graph coloring technique for low power, the proposed algorithm Proves the effect through various high level benchmark examples to adopt a multiple supply voltage scheduling algorithm for low power.

• Nuclear Engineering and Technology
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• v.40 no.7
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• pp.571-580
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• 2008

A Binary Decision Diagram (BDD) is a graph-based data structure that calculates an exact top event probability (TEP). It has been a very difficult task to develop an efficient BDD algorithm that can solve a large problem since it is highly memory consuming. In order to solve a large reliability problem within limited computational resources, many attempts have been made, such as static and dynamic variable ordering schemes, to minimize BDD size. Additional effort was the development of a ZBDD (Zero-suppressed BDD) algorithm to calculate an approximate TEP. The present method is the first successful application of a BDD truncation. The new method is an efficient method to maintain a small BDD size by a BDD truncation during a BDD calculation. The benchmark tests demonstrate the efficiency of the developed method. The TEP rapidly converges to an exact value according to a lowered truncation limit.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.104-114
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• 1995

In this paper, an intermediate representation HSFG(Hanyang Sequential Flow GRaph) and a new scheduling algorithm for the control-dominated ASIC design is presented. The HSFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. The scheduling algorithm minimizes the total operating time by reducing the number of the constraints as maximal as possible, searching a few paths among all the paths produced by conditional branches. The constraints are substitute by subgraphs, and then the number of subgraphs (that is the number kof the constraints) is minimized by using the inclusion and overlap relation among subgraphs. The proposed algorithm has achieved the better results than the previous ones on the benchmark data.

• ETRI Journal
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• v.43 no.4
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.795-807
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• 2005

The classical approaches for computing Live Variable Analysis(LVA) use iterative algorithms across the entire programs based on the Data Flow Analysis framework. In case of Zephyr compiler, average execution time of LVA takes $7\%$ of the compilation time for the benchmark programs. The classical LVA algorithm has many aspects for improvement. The iterative algorithm for LVA scans useless basic blocks and calculates large sets of variables repeatedly. We propose the improvement of Iterative algorithm for LVA based on used variables' upward movement. Our algorithm produces the same result as the previous iterative algorithm. It is based on use-def chain. Reordering of applying the flow equation in DFA reduces the number of visiting basic blocks and redundant flow equation executions, which improves overall processing time. Experimental results say that our algorithm ran reduce $36.4\%\;of\;LVA\;execution\;time\;and\;2.6\%$ of overall computation time in Zephyr compiler with benchmark programs.