• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.275-279
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• 2004

A new burst mode clock and data recovery circuit is realized that improves the previousldy-known gated-oscilletor technique with half rate clock recovery, The circuit was fabricated with 0.25um CMOS technology, and its functions were confirmed up to 1 Gbps.

• Journal of IKEEE
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• v.25 no.4
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• pp.721-727
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• 2021

This paper proposes a UWB (Ultar-wideband) impulse generator using the gated ring oscillator. The oscillator and PLL circuits which generate a several GHz LO signal for the conventional architecture are replaced with the gated ring oscillator. Therefore, the system complexity is decreased. The proposed architecture controls the duty of enable signal, which is used for the head switch of ring oscillator. The control of the duty enables to tun off the oscillator during the guard interval and stop wasting the power consumption. The pulse shaping method using the counter makes the small side lobe and preserves the bandwidth regardless of the change on the center frequency. Designed UWB impulse generator could change the center frequency from 6.0 GHz to 8.8 GHz with a digital bit control, while it preserves the bandwidth as about 1.5 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.