• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.176-176
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• 2010

One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio (Ion/Ioff), leakage current, threshold voltage, and hysteresis under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stability of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers was investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic-layer-deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to 105 times with 5mm bending radius. In the most of the devices after 105 times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the Ion/Ioff and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.173-181
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• 1992

Tantalum pentoxide($Ta_{2}O_{5}$) thin films on p-type (100) silicon wafer were fabricated by RF reactive sputtering. Physical properties and structure of the specimens were examined by XRD and AES. From the C-V analysis, the dielectric constant of $Ta_{2}O_{5}$ films was in the range of 10-12 in the reactive gas atmosphere in which 10% of oxygen gas is mixed. The ratio of Ta : 0 was 1 : 2 and 1 : 2.49 by AES and RBS examination, respectively. The heat-treatment at $700^{\circ}C$ in $O_{2}$ ambient led to induce crystallization. When the heat-treatment temperature was $1000^{\circ}C$, the dielectric constant was 20.5 in $O_{2}$ ambient and 23 in $N_{2}$ ambient, respectively. The crystal structure of $Ta_{2}O_{5}$ film was pseudo hexagonal of ${\delta}-Ta_{2}O_{5}$. The flat band voltage shift(${\Delta}V_{FB}$) of the specimens and the leakage current density were decreased for higher oxygen mixing ratio. The maximum breakdown field was 2.4MV/cm at the oxygen mixing ratio of 10%. The $Ta_{2}O_{5}$ films will be applicable to hydrogen ion sensitive film and gate oxide material for memory device.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.8
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• pp.5513-5521
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• 2015

There is an operational efficiency problem about wayside equipment applied to the domestic low-density branch as the equipment has been installed and operated similarly in the mainline. On-board oriented train control system, which has been developed for train safety and operation efficiency, ensures safe train operation without expensive ground control signal devices. Such system consists of on-board control system, wayside control system, and local control system. In this paper, the details of tests such as suitability test, communication test, and interface test are described by installing the on-board control system and wayside control system in field. Installation tests include checking power, voltage, cable connection, LED status, etc. Field applicability of the developed system is also verified through the dynamic operation tests with diverse scenarios, which are performed on the virtual line similar to the real environment including switch machine and level crossing gate. Dynamic operation tests were conducted for total 7 scenarios, and several tests were repeated for each scenario. The elapsed time for each operation was computed by analyzing main process log, and we could check that each operation was accomplished within several seconds. Furthermore, the developed system was verified through field test with an accredited institute, and testing certificates were issued.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1104-1109
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• 2005

In this paper, a Ka-band harmonic mixer is designed and fabricated on the base of the multiplier theory that there is a bias point to maximize the third harmonic order($3f_{LO}$) with respect to a fundamental LO frequency($f_{LO}$), which can make the high-order mixing element($f_{RF}{\pm}3f_{LO}$) to be greater than other mixing elements, Pumping a RF frequency($f_{RF}$) and LO frequency($f_{LO}$). The harmonic mixer by the proposed design method is fabricated by using a commercial GaAs MESFET device with a plastic package and overcome these disadvantages that a conventional mixer in Ka-band suffer from a high cost, inefficient productivity and circuit complexity. The harmonic mixer have a -10 dB conversion loss at the IF Sequency($3f_{LO}-f_{RF}$=1.0GHz) by selecting a gate bias voltage for the maximum third-order LO harmonic element($3f_{LO}$=34.5 GHz) as pumping LO frequency($f_{LO}$=11.5 GHz) With respect to RF Sequency ($f_{RF}$=33.5GHz)

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.2 s.302
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• pp.49-58
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• 2005

A new soft switching three-phase PWM rectifier with simple circuit configuration and high efficiency has been developed. The proposed circuit is a kind of the auxiliary resonant commutated Pole(ARCP)converter The conventional ARCP converter requires three-auxiliary reactors and six-auxiliary switches for the soft switching auxiliary circuit and for these switching elements, a gate drive circuit and a control circuit are required, resulting in high part as a disadvantage. In the main circuit proposed in this paper, the auxiliary soft switching circuit is composed of two-auxiliary reactors, two-auxiliary switches and several diodes. In addition, common use of the PWM control circuit for two-switches will make the control circuit of the auxiliary switches simple. By means of function of the soft switching auxiliary circuit, the main switching element performs zero voltage switching operation and the auxiliary switches perform the zero current switching. In this paper, the circuit configuration and the operational analysis of the proposed circuit are described at first and then, experimental results will be reported. By using a prototype with 5[kW] capacity, the conversion efficiency of maximum $98.8[\%]$ and the power factor of $99[\%]$ or higher were obtained.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.77-78
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• 2006

최근 flexible OLED의 구동에 사용하기 위한 유기박막트랜지스터(Organic Thin Film Transistor, OTFT)의 연구에서는 용매에 용해되어 spin coating이 가능한 재료의 개발에 관심을 두고 있다. 현재 pentacene으로는 아직 spin coating으로 제작할 수 있는 상용화된 제품이 없고 spin coating이 가능한 활성층 물질(active material)로 P3HT가 쓰이고 있다. 본 연구에서는 용해 가능한 P3HT 활성층 물질과 여러 종류의 용해 가능한 게이트 절연물(gate insulator, Gl)을 사용하여 안정된 소자를 구현할 수 있는 공정을 개발하는 목적으로 metal-insulator-semironductor(MIS) 소자를 제작하여 C-V 특성을 측정하고 분석하였다. 먼저 7mm${\times}$7mm 크기의 pyrex glass 시편 위에 바닥 전극으로 $1600{\AA}$ Au을 증착하고 spin coating 방식을 이용하여 PVP, PVA, PVK, BCB, Pl의 5종류의 게이트 절연층을 각각 형성하였고 그 위에 같은 방법으로 P3HT를 코팅하였다. P3HT 코팅 시 bake 공정의 유무와 spin rpm의 변화에 따른 P3HT의 두께를 측정하였다. Gl의 종류별로 주파수에 따른 capatltancc를 측정하여 비교, 분석하였다. C-V 측정 결과 PVP, PVA, PVK, BCB, Pl의 단위 면적당 capacitance 값은 각각 1.06, 2.73, 2.94, 3.43, $2.78nF/cm^2$로 측정되었다. Threshold voltage, $V_{th}$는 각각 -0.4, -0.7, -1.6, -0.1, -0.2V를 나타냈다. 주파수에 따른 capacitance 변화율을 측정한 결과 Gl 물질 모두 주파수가 높을수록 capacitance가 점점 감소하는 경향을 보였으나 1${\sim}$2nF 이내의 범위에서 작은 변화율만 나타냈다. P3HT의 두께와 bake 온도를 변화시켜 C-V 값을 측정한 결과 차이는 없었다. FE-SEM으로 관찰한 결과에서도 두께나 온도에 따른 P3HT의 표면 morphology 차이를 확인할 수 없었다. 본 연구에서 PVK와 P3HT의 조합이 수율(yield)면에서 가장 안정적이면서 $3.43\;nF/cm^2$의 가장 높은 capacitance 값을 나타내고 $V_{th}$ 값 또한 -1.6V로 가장 낮은 값을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of Biomedical Engineering Research
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• v.20 no.1
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• pp.107-113
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• 1999

The purpose of this study was to develop a miniature imaging gamma probe with high performance that can detect small or residual tumors after surgery. Gamma probe detector system consists of NaI(Tl) scintillator, position sensitive photomultiplier tube (PSPMT), and collimator. PSPMT was optically coupled with 6.5 mm thick, 7.62 cm diameter of NaI(Tl) crystal and supplied with -1000V for high voltage. Parallel hexagonal hole collimator was manufactured for characteristics of 40-mm hole length, 1.3-mm hole diameter, and 0.22 mm septal thickness. Electronics consist of position and trigger signal readout systems. Position signals were obtained with summing, subtracting, and dividing circuit using preamplifer and amplifier. Trigger signals were obtained using summing amplifier, constant fraction discriminator, and gate and delay generator module with preamplifer. Data acquisition and processing were performed by Gamma-PF interface board inserted into pentium PC and PIP software. For imaging studies, flood and slit mask images were acquired using a point source. Two hole phantom images were also acquired with collimator. Intrinsic and system spatial resolutions were measured as 3.97 mm and 5.97 mm, respectively. In conclusion, Miniature gamma probe images based on the PSPMT showed good image quality, we conclude that the miniature imaging gamma probe was successfully developed and good image data were obtained. However, further studies will be required to optimize imaging characteristics.