• Title/Summary/Keyword: gate voltage

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Simulation Study on a Quasi Fermi Energy Movement in the Floating Body Region of FITET (Field-induced Inter-band Tunneling Effect Transistor)

  • Song, Seung-Hwan;Kim, Kyung-Rok;Kang, Sang-Woo;Kim, Jin-Ho;Kang, Kwon-Chil;Shin, Hyung-Cheol;Lee, Jong-Duk;Park, Byung-Gook
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.679-682
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    • 2005
  • Negative-differential conductance (NDC) characteristics as well as negative-differential trans-conductance (NDT) characteristics have been observed in the room temperature I-V characteristics of Field-induced Inter-band Tunneling Effect Transistors (FITETs). These characteristics have been explained with inter-band tunneling physics, from which, inter-band tunneling current flows when the energy bands of degenerately doped regions align, and it does not flow when they don't. FITET is an SOI device and the body region is not directly connected to the external terminal. Therefore, Fermi energy in the body region is determined by electrical coupling among four regions - gate, source, drain and substrate. So, a quasi Fermi energy of the majority carriers in the floating body region can be changed by external voltages, and this causes the energy band movements in the body region, which determine whether the energy bands between degenerately doped junctions aligns or not. This is a key point for an explanation of NDT and NDC characteristics. In this paper, a quasi Fermi energy movement in the floating body region of FITET was investigated by a device simulation. This result was applied for the description of relation between quasi Fermi energy in the body region and external gate bias voltage.

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An Electrical Properties Analysis of CMOS IC by Narrow-Band High-Power Electromagnetic Wave (협대역 고출력 전자기파에 의한 CMOS IC의 전기적 특성 분석)

  • Park, Jin-Wook;Huh, Chang-Su;Seo, Chang-Su;Lee, Sung-Woo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.9
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    • pp.535-540
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    • 2017
  • The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

Multi-channel Transimpedance Amplifier Arrays in Short-Range LADAR Systems for Unmanned Vehicles (무인차량용 단거리 라이다 시스템을 위한 멀티채널 트랜스임피던스 증폭기 어레이)

  • Jang, Young Min;Kim, Seung Hoon;Cho, Sang Bock;Park, Sung Min
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.12
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    • pp.40-48
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    • 2013
  • This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

Floating Gate Organic Memory Device with Plasma Polymerized Styrene Thin Film as the Memory Layer (플라즈마 중합된 Styrene 박막을 터널링층으로 활용한 부동게이트형 유기메모리 소자)

  • Kim, Heesung;Lee, Boongjoo;Lee, Sunwoo;Shin, Paikkyun
    • Journal of the Korean Vacuum Society
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    • v.22 no.3
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    • pp.131-137
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    • 2013
  • The thin insulator films for organic memory device were made by the plasma polymerization method using the styrene monomer which was not the wet process but the dry process. For the formation of stable plasma, we make an effort for controlling the monomer with bubbler and circulator system. The thickness of plasma polymerized styrene insulator layer was 430 nm, the thickness of the Au memory layer was 7 nm thickness of plasma polymerized styrene tunneling layer was 30, 60 nm, the thickness of pentacene active layer was 40 nm, the thickness of source and drain electrodes were 50 nm. The I-V characteristics of fabricated memory device got the hysteresis voltage of 45 V at 40/-40 V double sweep measuring conditions. If it compared with the results of previous paper which was the organic memory with the plasma polymerized MMA insulation thin film, this result was greater than 18 V, the improving ratio is 60%. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make the organic memory device with plasma polymerized styrene as the memory thin film.

DEVELOPMENT OF AC SERVO MOTOR CONTROLLER FOR INDUSTRIAL ROBOT AND CNC MACHINE SYSTEM (산업용 ROBOT와 공작기계를 위한 AC SERVO MOTOR 제어기 개발)

  • Lim, Sang-Gwon;Lee, Jin-Won;Moon, Yong-Ky;Jeon, Dong-Lyeol;Jin, Sang-Hyun;Oh, In-Hwan;Kim, Dong-Il;Kim, Sung-Kwun
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.1211-1214
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    • 1992
  • AC servo motor drives, Fara DS series, proposed in this paper can be effectively used in robots, CNC machine tools, and FA system with AC servo motors as actuators. The inverter of the AC servo drive consists of IGBT (Insulated Gate Bipolar Transistor) which have high switching frequency. Noises and vibrations generated in variable speed control of AC servo motors can be greatly reduced due to their high switching frequencies. In the developed servo drive, maximum torque is always generated in the whole speed range by compensating phase shift, which results from the nonlinearies of the AC servo motor during abrupt acceleration and deceleration. Abundant protection functions are provided to prevent abnormal state of the servo motor, and furthermore diverse user options are considered provided for the effective application. The proposed AC servo motor drive is designed to minimize velocity variation with respect to external load, supply voltage, environmental temperature, and humidity, so can be widely used in the fields of factory automation including robots and CNC msachine tools.

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Design and Implementation of Digital Electrical Impedance Tomography System (디지털 임피던스 영상 시스템의 설계 및 구현)

  • 오동인;백상민;이재상;우응제
    • Journal of Biomedical Engineering Research
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    • v.25 no.4
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    • pp.269-275
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    • 2004
  • Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

저온 공정 온도에서 $Al_2O_3$ 게이트 절연물질을 사용한 InGaZnO thin film transistors

  • 우창호;안철현;김영이;조형균
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.11-11
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    • 2010
  • Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

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A Study on the Mobile Communication System for the Ultra High Speed Communication Network (초고속 정보통신망을 위한 이동수신 시스템에 관한 연구)

  • Kim, Kab-Ki;Moon, Myung-Ho;Shin, Dong-Hun;Lee, Jong-Arc
    • Journal of IKEEE
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    • v.2 no.1 s.2
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    • pp.1-14
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    • 1998
  • In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

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A Study on Modeling of Leakage Current in ESS Using PSCAD/EMTDC (PSCAD/EMTDC를 이용한 ESS의 누설전류 모델링에 관한 연구)

  • Kim, Ji-Myung;Tae, Dong-Hyun;Lee, Il-Moo;Lim, Geon-Pyo;Rho, Dae-Seok
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.22 no.2
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    • pp.810-818
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    • 2021
  • A leakage current of ESS is classified mainly by the occurrence from a PCS(Power Conditioning System) section and an unbalanced grid current. The reason for the leakage current from the PCS section is a voltage change by IGBT (Insulated Gate Bipolar Transistor) switching and stray capacitance between the IGBT and heatsink. The leakage current caused by the grid unbalanced current flows to the ESS through the neutral line of grid-connected transformer for the ESS with a three limb iron type of Yg-wire connection. This paper proposes a mechanism for the occurrence of leakage current caused by stray capacitance, which is calculated using the heatsink formula, from the aspect of the PCS section and grid unbalance current. Based on the proposed mechanisms, this study presents the modeling of the leakage current occurrence using PSCAD/EMTDC S/W and evaluates the characteristics of leakage currents from the PCS section and grid unbalanced current. From the simulation result, the leakage current has a large influence on the battery side by confirming that the leakage current from the PCS is increased from 7[mA] to 34[mA], and the leakage current from an unbalanced load to battery housing is increased from 3.96[mA] to 10.76[mA] according to the resistance of the housings and the magnitude of the ground resistance.

Analysis of Passing Word Line Induced Leakage of BCAT Structure in DRAM (BCAT구조 DRAM의 패싱 워드 라인 유도 누설전류 분석)

  • Su Yeon, Kim;Dong Yeong Kim;Je Won Park;Shin Wook Kim;Chae Hyuk Lim;So won Kim;Hyeona Seo;Ju Won Kim;Hye Rin Lee;Jeong Hyeon Yun;Young-Woo Lee;Hyoung-Jin Joe;Myoung Jin Lee
    • Journal of IKEEE
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    • v.27 no.4
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    • pp.644-649
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    • 2023
  • As the cell spacing decreases during the scaling process of DRAM(Dynamic Random Access Memory), the reduction in STI(Shallow Trench Isolation) thickness leads to an increase in sub-threshold leakage due to the passing word line effect. The increase in sub-threshold leakage current caused by the voltage applied to adjacent passing word lines affects the data retention time and increases the number of refresh operations, thereby contributing to higher power consumption in DRAM. In this paper, we identify the causes of the passing word line effect through TCAD Simulation. As a result, we confirm the DRAM operational conditions under which the passing word line effect occurs, and observe that this effect alters the proportion of the total leakage current attributable to different causes. Through this, we recognize the necessity to consider not only leakage currents due to GIDL(Gate Induced Drain Leakage) but also sub-threshold leakage currents, providing guidance for improving DRAM structure.