• ETRI Journal
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• 제31권6호
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• pp.653-659
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• 2009

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.59-69
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• 2002

A semi-analytical model based on exact numerical analysis of the 2DEG channel in pseudo-morphic HEMT (PMHEMT) is presented. The exactness of the model stems from solving both Schrodinger's wave equation and Poisson's equation simultaneously and self-consistently. The analytical modeling of the device terminal characteristics in relation to the charge control model has allowed a best fit with the geometrical and structural parameters of the device. The numerically obtained data for the charge control of the channel are best fitted to analytical expressions which render the problem analytical. The obtained good agreement between experimental and modeled current/voltage characteristics and small signal parameters has confirmed the validity of the model over a wide range of biasing voltages. The model has been used to compare both the performance and characteristics of a PMHEMT with a competetive HEMT. The comparison between the two devices has been made in terms of 2DEG density, transfer characteristics, transconductance, gate capacitance and unity current gain cut-off frequency. The results show that PMHEMT outperforms the conventional HEMT in all considered parameters.

• 대한전자공학회논문지SD
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• 제41권10호
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• pp.17-22
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• 2004

본 논문에서는 진폭 변조와 펄스 폭 변조를 모두 사용하는 새로운 AMOLED 디스플레이 구동 방식을 개발하였다. 펄스 폭 변조를 위해서 다섯 개의 서브 프레임으로 화상 프레임을 나누었고 진폭 변조를 위해 TFT 게이트 전압에 의해 제어되는 3가지의 OLED 휘도(전류) 레벨을 사용하였다. 이 두 종류의 변조를 조합하여 35(=243) 계조를 얻었다. 그리고 DAC를 사용하지 않고 2개의 쉬프트 레지스터를 갖는 새로운 데이터 전극 구동 회로를 설계하였다. 회로 동작은 6㎛ 채널 길이 다결정 TFT의 전류-전압 특성에서 추출된 TFT 파라미터를 이용한 HSpice 시뮬레이션을 통하여 검증하였다. 시뮬레이션 결과로부터 320×240, 이중 스캔, 243 계조 AMOLED 디스플레이를 구현할 수 있음을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.818-823
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• 2014

A high-gain wideband low noise amplifier (LNA) using $0.25-{\mu}m$ Gallium-Nitride (GaN) MMIC technology is presented. The LNA shows 8 GHz to 15 GHz operation by a distributed amplifier architecture and high gain with an additional common source amplifier as a mid-stage. The measurement results show a flat gain of $25.1{\pm}0.8dB$ and input and output matching of -12 dB for all targeted frequencies. The measured minimum noise figure is 2.8 dB at 12.6 GHz and below 3.6 dB across all frequencies. It consumes 98 mA with a 10-V supply. By adjusting the gate voltage of the mid-stage common source amplifier, the overall gain is controlled stably from 13 dB to 24 dB with no significant variations of the input and output matching.

• 한국전기전자재료학회논문지
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• 제22권9호
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• pp.737-740
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.182-183
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• 2008

We fabricated a pentacene thin film transistor with Poly-vinylalcohol (PVA) as a dielectric. And we used Poly(9-vinylcarbazole) (PVK) as a buffer layer to improve the electrical characteristics. PVK is a material used often host material for OLED device, as it has good film forming properties, large HOMO-LUMO(highest occupied molecular orbital-lowest unoccupied molecular orbital) bandgap. The performance of a OTFT device with PVA gate dielectric was improved by using the PVK. Field effect mobility, threshold voltage, and on-off current ratio of device with PVK layer were about 0.6 $cm^2$/Vs, -17V, and $5\times10^5$, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.200-201
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• 2017

이 논문은 3D 순차적 CMOS 인버터 회로의 전기적 상호작용을 고려한 시뮬레이션을 제시하고자 한다. 상층 NMOS는 BSIM-IMG, 하층 PMOS에는 LETI-UTSOI 모델을 사용하여 전기적 상호작용이 잘 반영되는지 TCAD 데이터와 SPICE 데이터를 비교하였다. 트랜지스터 간의 높이가 작을 때 하층 게이트의 전압의 변화에 따라 상층 전류-전압 특성에 전기적 상호작용이 잘 반영되는 것을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.998-1001
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• 2009

A new flexible TFT backplane structure with improved mechanical reliability is proposed. Amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors based on this structure have been fabricated on a polyimide substrate, and the resultant mechanical durability has been evaluated in a cyclic bending test. The panel can withstand 10,000 bending cycles at a bending radius of 5 mm without any noticeable TFT degradation. After 10K bending cycles, the change of threshold voltage, mobility, sub-threshold slope, and gate leakage current were only -0.22V, -0.13$cm^2$/V-s, -0.05V/decade, and $-3.05{\times}10^{-13}A$, respectively.

• 한국통신학회논문지
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• 제25권8B호
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• pp.1469-1476
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• 2000

증가형 MOS FET에서 강반저의 경우 드레인 전류는 모두 드리프트에 기인하여 흐르기 때문에 I-V모델링시 수직전계와 수평전계를 함께 고려하여야한다. 특히 게이트전압 인가시 발생되는 수직전계는 표면이동도에 영향을 크게 주고 이로 인해서 캐리어들의 정상적인 흐름이 저해되는데 본 논문에서 제안한 다중 box분할법에 의하여 반전층의 깊이를 구하여 이동도 모델에 영향을 크게 미치는 반전층 내에서의 수직전계를 수치해석하였다.