• 제목/요약/키워드: gate resistance

검색결과 355건 처리시간 0.029초

Ti/Au, Ti/Pd/Au 쇼트키 접촉의 열처리에 따른 GaAs MESFET의 전기적 특성 (Electrical characteristics of GaAs MESFET according to the heat treatment of Ti/Au and Ti/Pd/Au schottky contacts)

  • 남춘우
    • E2M - 전기 전자와 첨단 소재
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    • 제8권1호
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    • pp.56-63
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    • 1995
  • MESFETs of the Ti/Au and Ti/Pd/Au gate were fabricated on n-type GaAs. Interdiffusion at Schottky interfaces, Schottky contact properties, and MESFET characteristics with heat treatment were investigated. Ti of Ti/Au contact and Pd of Ti/Pd/Au contact acted as a barrier metal against interdiffusion of Au at >$220^{\circ}C$. Pd of Ti/Pd/Au contact acted as a barrier metal even at >$360^{\circ}C$, however, Ti of Ti/Au contact promoted interdiffusion of Au instead of role of barrier metal. As the heat treatment temperature increases, in the case of both contact, saturated drain current and pinch off voltage decreased, open channel resistance increased, and degree of parameter variation in Ti/Au gate was higher than in Ti/Pd/Au gate at >$360^{\circ}C$ Schottky barrier height of Ti/Au and Ti/Pd/Au contacts was 0.69eV and 0.68eV in the as-deposited state, respectively, and Fermi level was pinned in the vicinity of 1/2Eg. As the heat treatment temperature increases, barrier height of Ti/Pd/Au contact increased, however, decreased at >$360^{\circ}C$ in the case of Ti/Au contact. Ideality factor of Ti/Au contact was nearly constant regardless of heat treatment, however, increased at >$360^{\circ}C$ in the case of Ti/Au contact. From the results above, Ti/Pd/Au was stable gate metal than Ti/Au.

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실리콘 게이트 n-well CMOS 소자의 제작, 측정 및 평가 (Fabrication, Mesurement and Evaluation of Silicon-Gate n-well CMOS Devices)

  • 류종선;김광수;김보우
    • 대한전자공학회논문지
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    • 제21권5호
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    • pp.46-54
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    • 1984
  • 3μm 게이트 길이를 가지는 n-well CMOS 공정이 개발되었고 이의 응용 가능성을 검토하였다. Thres-hold 전압은 이온주입으로 쉽게 조절할 수 있으며, 3μm 채널 길이에서 short 채널 효과는 무시할 수 있다. Contact 저항에 있어서 Al-n+ 저항값이 커서 VLSI 소자의 제작에 장애 요인이 될 것으로 보인다. CMOS inverter의 transfer 특성은 양호하며, (W/L) /(W/L) =(10/5)/(5/5)인 89단의 ring oscillator로부터 구한 게이트당 전달 지연 시간은 3.4nsec 정도이다. 본 공정의 설계 규칙에서 n-well과 p-substrate에 수 mA의 전류가 흐를 때 latch-up이 일어나며, well 농도와 n+소오스-well간의 간격에 크게 영향을 받는다. 따라서 공정과 설계 규칙의 변화에 따른 latch-up 특성에 집중적인 연구가 필요할 것으로 사료된다.

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P3HT와 IZO 전극을 이용한 thin film transistors 제작 (Fabricated thin-film transistors with P3HT channel and $NiO_x$ electrodes)

  • 강희진;한진우;김종연;문현찬;박광범;김태하;서대식
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.467-468
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    • 2006
  • We report on the fabrication of P3HT-based thin-film transistors (TFT) that consist of indium-zinc-oxide (IZO), PVP (poly-vinyl phenol), and Ni for the source-drain (S/D) electrode, gate dielectric, and gate electrode, respectively. The IZO S/D electrodes of which the work function is well matched to that of P3HT were deposited on a P3HT channel by thermal evaporation of IZO and showed a moderately low but still effective transmittance of ~25% in the visible range along with a good sheet resistance of ${\sim}60{\Omega}/{\square}$. The maximum saturation current of our P3HT-based TFT was about $15{\mu}A$ at a gate bias of -40V showing a high field effect mobility of $0.05cm^2/Vs$ in the dark, and the on/off current ratio of our TFT was about $5{\times}10^5$. It is concluded that jointly adopting IZO for the S/D electrode and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

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미세 구조물의 충전에 관한 실험 및 수치해석 (Experimental & Numerical Result of the filling of Micro Structures in Injection Molding)

  • 이재구;이봉기;권태헌
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 추계학술대회 논문집
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    • pp.111-114
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    • 2005
  • Experimental and numerical studies were carried out in order to investigate the processability and the transcriptability of the injection molding of micro structures. For this purpose, we designed a mold insert having micro rib patterns on a relatively thick base part. Mold insert has a base of 2mm thickness, and has nine micro ribs on that base plate. Width and height of the rib are $300{\mu}m\;and\;1200{\mu}m$, respectively. We found a phenomenon similar to 'race tracking', due to 'hesitation' in the micro ribs. As the melt flows, it starts to cool down and melt front located in the ribs near the gate cannot penetrate further because the flow resistance is large in that almost frozen portion. When the base is totally filled, the melt front away from the gate is not frozen yet. Therefore, it flows back to the gate direction through the ribs. Consequently, transcriptability of the rib far from the gate is better. We also verified this phenomenon via numerical simulation. We further investigated the effects of processing conditions, such as flow rate, packing time, packing pressure, wall temperature and melt temperature, on the transcriptability. The most dominant factor that affects the flow pattern and the transcriptability of the micro rib is flow rate. High flow rate and high melt temperature enhance the transcriptability of micro rib structure. High packing time and high packing pressure result in insignificant dimensional variations of the rib. Numerical simulation also confirms that low flow rate causes a short shot of micro ribs and high wall temperature helps the filling of the micro ribs.

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강철재 도어의 내화, 기밀성 향상을 위한 이중틈새 차단장치에 관한 연구 (A Study on the Double Gap Blocking Device for the Improvement of Fire Resistance and Airtightness of Steel Door)

  • 이주원;임보혁;조성권;이해열
    • 한국건축시공학회:학술대회논문집
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    • 한국건축시공학회 2023년도 봄 학술논문 발표대회
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    • pp.147-148
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    • 2023
  • Steel doors, which are common in general buildings, do not seal the gap between the door and the floor, so drafts, noise, dust, and lights flow from the outside, and shielding devices are installed in various materials and methods, such as adding magnetic gate paper to the side of the door or installing a gasket under the door, but performance is limited. Accordingly, in order to fundamentally solve these problems, we researched and developed a double gap blocking device that can improve fire resistance and airtightness performance in steel doors. Unlike general products, the double gap blocking device has the advantage of maximizing airtight performance by forming an air layer in the center when the door is closed, as well as greatly improving the fire resistance performance, which is the basic performance of the fire door.

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Three Dimensional Architecture of Multiplexing Data Registration Integrated Circuit for Flat Panel Display

  • Tseng, Fan-Gang;Liou, Jian-Chiun
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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    • pp.1293-1296
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    • 2008
  • As Flat Panel Display become large in format, the data and gate lines turn into longer, parasitic capacitance and resistance increase, and the display signal is delayed. Three dimensional architecture of multiplexing data registration integrated circuit method is used that divides the data line into several blocks and provides the advantages of high accuracy, rapid selection, and reasonable switching speed.

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Downscaling of self-aligned inkjet printed polymer thin film transistors

  • Noh, Yong-Young;Sirringhaus, Henning
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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    • pp.1564-1567
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    • 2008
  • We demonstrate here a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 - 400 nm. A perfected down-scaled polymer transistors (L= 200 nm) showing high transition frequency over 1.5 Mhz were realized with thin polymer dielectrics, controlling contact resistance, and minimizing overlap capacitance via self-aligned gate configuration.

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MOSFET 기생성분 모델링 (Pad and Parasitic Modeling for MOSFET Devices)

  • 최용태;김기철;김병성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 추계종합학술대회 논문집
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    • pp.181-184
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    • 1999
  • This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

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Novel Method to Form Metal Electrodes by Self-Alignment and Self-Registration Processes

  • Shin, Dong-Youn
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1197-1199
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    • 2009
  • Self-alignment for the fabrication of printed thin film transistors has become of great interest because of the resolution and registration limits of printing technologies. In this work, self-patterning and selfregistration processes are introduced, which do not need surface energy patterning and the resulting minimum gate channel length could be down to $11.2{\mu}m$ with the sheet resistance of 2.6 ${\Omega}/{\square]$ for the source and drain electrodes.

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지구물리탐사를 이용한 경산시 환성사 일주문 지반조사 (Geophysical exploration for the Site Charcteristics of Iljumun Gate in Hwanseongsa Temple)

  • 김기현;서만철
    • 한국지구물리탐사학회:학술대회논문집
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    • 한국지구물리탐사학회 2008년도 공동학술대회
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    • pp.131-136
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    • 2008
  • 일주문 주변 지반의 지반 구조 및 상태를 파악하고 복원시 보존, 보수의 방향 및 설계자료를 제공하기 위해, 탄성파 탐사, 전기비저항탐사, 평판재하시험 등의 비파괴 지구물리탐사를 수행하였다. 전기비저항탐사결과, 전반적인 전기비저항분포는 50-1300 ohm-m의 범위를 보여주고 있다. 또한 일주문 석주 남쪽 1m, 석주 3번과 4번 사이, 석주 2번과 3번 북쪽 1m 위치에서 주위보다 비교적 낮은 전기비저항 이상을 보여주고 있다. 석주 3번과 4번 사이에서 나타나는 낮은 전기비저항 이상은 탄성파 반사법 탐사결과에서 나타나는 이상구간과 일치함을 보여주고 있다. 평판재하시험 결과 허용지지력은 $10.70tf/m^2$이상이며, 이때의 침하량은 19.635mm로 산정되었다. 일주문 복원시 설계하중은 가정치를 적용하여 계산한 결과 $16.37t/m^2$로 계산되었으며, 이는 허용지지력을 훨씬 상회하므로 기초지반에 대한 강화대책이 반드시 필요한 것으로 판단된다.

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