• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.998-1001
• /
• 2009

A new flexible TFT backplane structure with improved mechanical reliability is proposed. Amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors based on this structure have been fabricated on a polyimide substrate, and the resultant mechanical durability has been evaluated in a cyclic bending test. The panel can withstand 10,000 bending cycles at a bending radius of 5 mm without any noticeable TFT degradation. After 10K bending cycles, the change of threshold voltage, mobility, sub-threshold slope, and gate leakage current were only -0.22V, -0.13$cm^2$/V-s, -0.05V/decade, and $-3.05{\times}10^{-13}A$, respectively.

• ETRI Journal
• /
• v.42 no.5
• /
• pp.773-780
• /
• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1994.05a
• /
• pp.116-119
• /
• 1994

The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.751-754
• /
• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of IKEEE
• /
• v.23 no.2
• /
• pp.375-379
• /
• 2019

$ZnO-SnO_2(ZTO)$ was deposited by RF magnetron sputtering using a ceramic target whose Zn atomic ratio to Sn is 2:1 as a target, and the crystal structure variation with thermal treats was investigated. Transparent thin film transistors (TTFT) were fabricated using the ZTO films as active layers. About 100 nm-thick $Si_3N_4$ film grown on 100 nm-thick $SiO_2$ film was adopted as gate dielectrics. The mobility, threshold voltage, $I_{on}/I_{off}$, and interface trap density were obtained from the transfer characteristics of ZTO TTFTs. The effects of substrate temperature, and post-annealing on the property variation of ZTO TTFT were analyzed.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
• /
• v.25 no.1
• /
• pp.1-10
• /
• 2019

Environmental evaluation of two different oxygen high barrier films were performed using life cycle assessment. One of the films (traditional film) was composed of aluminum oxide coated PET film, ink, LDPE and LLDPE. Another film (new film) was consists of PET, ink, protein based coating material, LDPE, LLDPE. Main layer to achieve the high oxygen barrier for traditional film was aluminum oxide coated PET film, whereas the protein based coating material act as oxygen barrier layer for new film. Functional unit of this study was 1000 pouches made of traditional and new film. System boundary was factory to gate. The results of this study revealed that the new film shows better environmental performance for most of impact indicator than traditional film, except marine eutrophication and fine particulate matter formation due to extra coating process in new film system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.2
• /
• pp.85-90
• /
• 2012

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.5
• /
• pp.46-51
• /
• 1989

The degradation phenomena induced by hot-carrier injection was studied from the shift of threshold voltage and subthreshold current curve in LDD NMOSFET degraded under different DC stress-biases. Threshold voltage shift ${Delta}V_{tex}$ defined in saturation region was separated into contri butions due to trapped oxide charge $V_{ot}$ and interface traps ${Delta}V_{it}$ generated from midgap to threshold voltage. Under th positive stress electric field (TEX>$V_g>V_d$) condition, the shift of threshold voltage was attributed to the electrons traped ar gate oxide but subthreshold swing was not negative stress electric field ($V_g) condition, holes seems to be injected positive charges so threshold voltage and subthreshold swing were increased.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.2 no.3
• /
• pp.431-437
• /
• 1998

In this paper, we have investigated the electrical properties of ultra-thin nitrided oxide(NO) and re-oxidized nitrided oxide(ONO) films that are considered to be promising candidates for replacing conventional silicon dioxide film in ULSI level integration. Especially, we have studied a variation of I-V characteristics, gate voltage shift, and time-dependent dielectric breakdown(TDDB) of thin layer NO and ONO film depending on nitridation and reoxidation time, respectively, and measured a variation of leakage current and charge-to-breakdown(Q$\_bd$) of optimized NO and ONO film depending on ambient temperature, and then compared with the properties of conventional SIO$\_2$. From the results, we find that these NO and ONO thin films are strongly influenced by process time and the optimized ONO film shows superior dielectric characteristics, and (Q$\_bd$) performance over the NO film and SIO$\_2$, while maintaining a similar electric field dependence compared with NO layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.292-295
• /
• 2004

The SIT was introduced by Nishizawa. in 1972. When compared with high-voltage, power bipolar junction transistors, SITs have several advantages as power switching devices. They have a higher input impedance than do bipolar transistors and a negative temperature coefficient for the drain current that prevents thermal runaway, thus allowing the coupling of many devices in parallel to increase the current handling capability. Furthermore, the SIT is majority carrier device with a higher inherent switching speed because of the absence of minority carrier recombination, which limits the speed of bipolar transistors. This also eliminates the stringent lifetime control requirements that are essential during the fabrication of high-speed bipolar transistors. This results in a much larger safe operating area(SOA) in comparison to bipolar transistors. In this paper, vertical SIT structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. A trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. The proposed devices have superior electrical characteristics when compared to conventional device. Consequently, the fabrication of trench oxide power SIT with superior stability and electrical characteristics is simplified.