• ETRI Journal
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• v.20 no.1
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• Journal of Power Electronics
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• v.12 no.6
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• pp.954-959
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• 2012

A hybrid switch that uses a microelectromechanical system (MEMS) switch as a gate driver of a MOSFET is applied to an energy harvesting system. The power management circuit adopting the hybrid switch provides ultralow leakage, self-referencing, and high current handling capability. Measurements show that solar energy harvester circuit utilizing the MEMS-MOSFET hybrid switch accumulates energy and charges a battery or drive a resistive load without any constant power supply and reference voltage. The leakage current during energy accumulation is less than 10 pA. The power management circuit adopting the proposed hybrid switch is believed to be an ideal solution to self-powered wireless sensor nodes in smart grid systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.540-548
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• 2007

The parer proposes a power factor correction high efficiency PWM single-phase rectifier. Its good characteristics such as simple PWM control, low switch stress, and low VAR rating of commutation circuits make the proposed rectifier very suitable for various unidirectional power applications. In addition, the proposed rectifier consists of three boost-converter-type IGBT modules with the switching devices located at the bottom leg of the rectifier scheme, which also enables the use of the same power supply in both control and gate driver, thus resulting in simple control and power circuit structure. The detailed principle of operation and experimental results are also included. In particular, the design guide line is also suggested to make the circuit design of the proposed rectifier easy and fast.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.71-79
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• 2010

This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.