• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.595-596
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and low-temperature processes. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing which is high-resolution lithography technology using polydimethylsiloxane(PDMS) stamp. The OTFT array with dielectric layer and organic active semiconductor layers formed at room temperature or at a temperature tower than $40^{\circ}C$. The microcontact printing process using SAM(self-assembled monolayer) and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even nano size, and reduced the procedure by 10 steps compared with photolithography. Since the process was done in low temperature, there was no pattern transformation and bending problem appeared. It was possible to increase close packing of molecules by SAM, to improve electric field mobility, to decrease contact resistance, and to reduce threshold voltage by using a big dielecric.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.287-287
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• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.264-264
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• 2011

1T-1C로 구성되는 기존의 dynamic random access memory (DRAM)는 데이터를 저장하기 위해 적절한 커패시턴스를 확보해야 한다. 따라서 커패시터 면적으로 인한 집적도의 한계에 직면해있으며, 이를 대체하기 위한 새로운 DRAM인 1T- DRAM이 연구되고 있다. 기존의 DRAM과 달리 silicon-on-insulator (SOI) 기술을 이용한 1T-DRAM은 데이터 저장을 위한 커패시터가 요구되지 않는다. 정공을 채널의 중성영역에 축적함으로서 발생하는 포텐셜 변화를 이용하며, 이때 발생하는 드레인 전류차를 이용하여 '0'과 '1'을 구분한다. 기존의 완전공핍형 평면구조의 1T-DRAM은 소스 및 드레인 접합부분에서 발생하는 누설전류로 인해 '0' 상태의 메모리 유지특성이 열화되는 단점을 가지고 있다. 따라서 메모리의 보존특성을 향상시키기 위해 소스/드레인 접합영역을 줄여 누설전류를 감소시키는 구조를 갖는 1T-DRAM의 연구가 필요하다. 또한 고유전율을 가지는 Si3N4를 이용한 oxide-nitride-oxide (ONO)구조의 게이트 절연막을 이용하면 동일한 두께에서 더 낮은 equivalent oxide thickness (EOT)를 얻을 수 있기 때문에 보다 저 전압에서 1T-DRAM 동작이 가능하여 기존의 SiO2 단일층을 이용한 1T-DRAM보다 동일 전압에서 더 큰 sensing margin을 확보할 수 있다. 본 연구에서는 누설전류를 감소시키기 위하여 소스 및 드레인이 채널위로 올려진 recessed channel 구조에 ONO 게이트 절연막을 적용한 1T-DRAM을 제작 및 평가하고, 본 구조의 1T-DRAM적용 가능성 및 ONO구조의 게이트 절연막을 이용한 sensing margin 개선을 확인하였다.

• 한국전기전자재료학회논문지
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• 제18권11호
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• pp.977-982
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• 2005

Al/AlN/n-type 6H-SiC (0001) MIS structures were prepared by AlN layers on vicinal 6H-SiC(0001) substrates with reactive RF magnetron sputtering method. The AlN films were annealed at $900^{\circ}C$, $N_2$ atmosphere lot 1 minutes showed the best result. With XRD analysis, AlN(0002) peak was clearly found. The typical dielectric constant value of the AlN film in the MIS capacitors was obtained as 8.4 from photo C-V. Also, the gate leakage current density of the MlS capacitor was $10^{-10}\;A/cm^2$ order within the electric field of 1.8 MV/cm. Finally, the amount of interface trap densities, $D_{it}$, was evaluated as $5.3\times10^{10}\;eV^{-1}cm^{-2}$ at (Ec-0.85) eV.

• Journal of Magnetics
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• 제8권1호
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• pp.24-31
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• 2003

The discoveries of antiferromagnetic coupling in Fe/Cr multilayers by Grunberg, the Giant Magneto Resistance by Fert and Grunberg and a large tunneling magnetoresistance at room temperature by Moodera have triggered enormous research on magnetic thin films and magnetoelectronic devices. Large opportunities are especially opened by the spin dependent tunneling resistance, where a strong dependence of the tunneling current on an external magnetic field can be found. We will briefly address important basic properties of these junctions like thermal, magnetic and dielectric stability and discuss scaling issues down to junction sizes below 0.01 $\mu\textrm{m}$$^2$with respect to single domain behavior, switching properties and edge coupling effects. The second part will give an overview on applications beyond the use of the tunneling elements as storage cells in MRAMs. This concerns mainly field programmable logic circuits, where we demonstrate the clocked operation of a programmed AND gate. The second 'unconventional' feature is the use as sensing elements in DNA or protein biochips, where molecules marked magnetically with commercial beads can be detected via the dipole stray field in a highly sensitive and relatively simple way.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.200-201
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• 2017

이 논문은 3D 순차적 CMOS 인버터 회로의 전기적 상호작용을 고려한 시뮬레이션을 제시하고자 한다. 상층 NMOS는 BSIM-IMG, 하층 PMOS에는 LETI-UTSOI 모델을 사용하여 전기적 상호작용이 잘 반영되는지 TCAD 데이터와 SPICE 데이터를 비교하였다. 트랜지스터 간의 높이가 작을 때 하층 게이트의 전압의 변화에 따라 상층 전류-전압 특성에 전기적 상호작용이 잘 반영되는 것을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.155-158
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• 2007

Printed organic thin-film transistor(OTFT) to use as a switching device for an organic light emitting diode(OLED) were fabricated in the microcontact printing and direct printing processes at room temperature. The gate electrodes($5{\mu}m$, $10{\mu}m$, and $20{\mu}m$) of OTFT was fabricated using microcontact printing process, and source/drain electrodes ($W/L=500{\mu}m/5{\mu}m$, $500{\mu}m/10{\mu}m$, and $500{\mu}m/20{\mu}m$) was fabricated using direct printing process with hard poly(dimethylsiloxane)(h-PDMS) stamp. Printed OTFT with dielectric layer was formed using special coating system and organic semiconductor layer was ink-jet printing process. Microcontact printing and direct printing processes using h-PDMS stamp made it possible to fabricate printed OTFT with channel lengths down to $5{\mu}m$, and reduced the process by 20 steps compared with photolithography. As results of measuring he transfer characteristics and output characteristics of OTFT fabricated with the printing process, the field effect characteristic was verified.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.