• Title/Summary/Keyword: gate circuit noise

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Single-bias GaAs MMIC single-ended mixer for cellular phone application (Cellular phone용 단일 전원 MMIC single-ended 주파수 혼합기 개발)

  • 강현일;이상은;오재응;오승건;곽명현;마동성
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.10
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    • pp.14-23
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    • 1997
  • An MMIC downconverting mixer for cellular phone application has been successfully developed using an MMIC process including $1 \mu\textrm{m}$ ion implanted gaAs MESFET and passive lumped elements consisting of spiral inductor, $Si_3N_4$ MIM capacitor and NiCr resistor. The configuration of the mixer presented in this paper is single-ended dual-gate FET mixer with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit is $1.4 mm \times 1.03 mm $ including all input matching circuits and a mixing circuit. The conversion gian and noise figure of the mixer at LO powr of 0 dBm are 5.5dB and 19dB, respectively. The two-tone IM3 characteristics are also measured, showing -60dBc at RF power of -30dBm. Allisolations between each port show better than 20dB.

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Design of MMIC Low Noise Amplifier for B-WLL using GaAs PHEMT (GaAs PHEMT를 이용한 B-WLL용 MMIC 저잡음 증폭기의 설계)

  • 김성찬;이응호;조희철;조승기;김용호;이진구
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.1
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    • pp.102-109
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    • 2000
  • In this paper, a Low Noise Amplifier for B-WLL was designed using the MMIC technology with GaAs PHEMTs fabricated at our lab. The PHEMT for LNA has a $0.35\mu\textrm{m}$ gate and a total gate width of $120\mu\textrm{m}$. The designed MMIC LNA consists of three stages. The first stage of the LNA has a series inductive feedback for obtaining minimum noise and high stability as well. And the designed MMIC LNA has not an interstage matching circuit between the second and the third stage for minimization of the chip size. From simulation results, noise figure and S21 gain of the designed MMIC LNA are 0.85~1.25 dB and 22.08~23.65 dB in the frequency range of 25.5~27.5 GHz respectively. And the chip size is $3.7\times1.6 mm^2$.

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Analysis on the Noise Factors of Static Induction Photo-Transistor (SIPT) (1) - The SIPT's Equivalent Circuits for the Analysis on the Noise Factors - (정전유도(靜電誘導) 포토 트랜지스터의 잡음(雜音) 원인(原因) 분석(分析) (1) - 잡음(雜音) 원인(原因) 분석(分析)을 위한 SIPT 등가회로(等價回路) -)

  • Kim, Jong-Hwa
    • Journal of Sensor Science and Technology
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    • v.4 no.4
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    • pp.29-40
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    • 1995
  • In this paper, the noise equivalent cicuits that is necessary to the formulation of D.C. and noise characteristics, residual component and input capacitance so as to analyze on the noise factors of the SIT is proposed. The simplest noise equivalent circuit is the model representing the mechanism of the SIT and the measured values in this model were found as small as the values of the shot-noise. In the source resistance inserted equivalent circuit is conformed that the shot-noise will be reduced by the negative-feedback effect of the source resistance. In oder to analyze the correct noise reduction factor, I proposed the equivalent circuit which the formulas of the source and drain resistance was induced. In the experiment which affirm the equivalent circuits, the influence of the signal source resistance and output load resistance on the residual component is small and the residual component can be expressed by the equivalent input noise resistance. Moreover, the input capacitance is 13.6 pF when the load resistance is $0{\Omega}$ and the capacitance which does not concern with the SIT operation directly, that is, gate wire etc, is 10pF or so.

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A 30 GHz Band Low Noise for Satellite Communications Payload using MMIC Circuits (MMIC 회로를 이용한 위성중계기용 30GHz대 저잡음증폭기 모듈 개발)

  • 염인복;김정환
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.796-805
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    • 2000
  • A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

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A Low-Power Register File with Dual-Vt Dynamic Bit-Lines driven by CMOS Bootstrapped Circuit

  • Lee, Hyoung-Wook;Lee, Hyun-Joong;Woo, Jong-Kwan;Shin, Woo-Yeol;Kim, Su-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.3
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    • pp.148-152
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    • 2009
  • Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

A Design of 5.8 ㎓ Oscillator using the Novel Defected Ground Structure

  • Joung, Myoung-Sub;Park, Jun-Seok;Lim, Jae-Bong;Cho, Hong-Goo
    • Journal of electromagnetic engineering and science
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    • v.3 no.2
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    • pp.118-125
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    • 2003
  • This paper presents a 5.8-㎓ oscillator that uses a novel defected ground structure(DGS), which is etched on the metallic ground plane. As the suggested defected ground structure is the structure for mounting an active device, it is the roles of a feedback loop inducing a negative resistance as well as a frequency-selective circuit. Applying the feedback loop between the drain and the gate of a FET device produces precise phase conversion in the feedback loop. The equivalent circuit parameters of the DGS are extracted by using a three-dimensional EM simulation ,md simple circuit analysis method. In order to demonstrate a new DGS oscillator, we designed the oscillator at 5.8-㎓. The experimental results show 4.17 ㏈m output power with over 22 % dc-to-RF power efficiency and - 85.8 ㏈c/Hz phase noise at 100 KHz offset from the fundamental carrier at 5.81 ㎓.

Studies on the High-gain Low Noise Amplifier and Module Fabrication for V-band (V-band 용 고이득 저잡음 증폭기와 모듈 제작에 관한 연구)

  • Baek, Yong-Hyun;Lee, Bok-Hyung;An, Dan;Lee, Mun-Kyo;Jin, Jin-Man;Ko, Du-Hyun;Lee, Sang-Jin;Lim, Byeong-Ok;Baek, Tae-Jong;Choi, Seok-Gyu;Rhee, Jin-Koo
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.583-586
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    • 2005
  • In this paper, millimeter-wave monolithic integrated circuit (MIMIC) low noise amplifier (LNA) for V-band, which is applicable to 58 GHz, we designed and fabricated. We fabricated the module using the fabricated LNA chips. The V-band MIMIC LNA was fabricated using the high performance $0.1\;{\mu}\;m$ ${\Gamma}-gate$ pseudomorphic high electron mobility transistor (PHEMT). The MIMIC LNA was designed using active and passive device library, which is composed $0.1\;{\mu}\;m$ ${\Gamma}-gate$ PHEMT and coplanar waveguide (CPW) technology. The designed V-band MIMIC LNA was fabricated using integrated unit processes of active and passive device. Also we fabricated CPW-to-waveguide fin-line transition of WR-15 type for module. The Transmission Line was fabricated using RT Duroid 5880 substrate. The measured results of V-band MIMIC LNA and Module are shown $S_{21}$ gain of 13.1 dB and 8.3 dB at 58 GHz, respectively. The fabricated LNA chip and Module in this work show a good noise figure of 3.6 dB and 5.6 dB at 58 GHz, respectively.

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A Study on Improving Mass Production of the Radar Sensor Oscillator (레이더 센서용 발진기의 양산성 향상에 관한 연구)

  • Kim, Byung-Chul;Cho, Kyung-Rae;Lee, Jae-Buom;Kim, Dae-Hyung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.4
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    • pp.669-676
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    • 2012
  • In this paper, The method to improve the mass production method of the radar sensor is suggested by using the temperature compensation circuit which is composed with the thermister. The mass production became easier by decreasing the adjustment time for the exact oscillation frequency with the temperature compensation circuit that can support the proper gate bias voltage for the FET after the dielectric resonator is removed from the DRO(Dielectric Resonator Oscillator) of the radar sensor. Radar sensor with the proposed method has 15.67MHz oscillator frequency variation in the temperature range of $-20^{\circ}C-+55^{\circ}C$, 0.65dB magnitude variation, -105.47dBc phase noise characteristics at 1MHz which are better or similar temperature characteristics with the DRO whose oscillator frequency variation is 25MHz, magnitude variation is 0.42dB and phase noise is -107.40dBc in the same temperature range.

Design of Temperature Compensation Circuit for W-band Radar Receiver (W-band 레이더 수신기용 온도보상회로 설계)

  • Lee, Dongju;Kim, Wansik;Kwon, Jun-Beom;Seo, Mihui;Kim, Sosu
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.4
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    • pp.129-133
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    • 2020
  • In this paper, a temperature compensation circuit is presented in order to mitigate gain variability due to temperature in the W-band low-noise amplifier (LNA). The proposed cascode temperature compensation bias circuit automatically controls gate bias voltages of the common-source LNA in order to suppress variations of small-signal gain. The designed circuit was realized in a 100-nm GaAs pHEMT process. The simulated voltage gain of W-band LNA including the proposed bias circuit is >20 dB with gain variability less than ±0.8 dB in the range of temperatures between -35 to 71℃. We expect that the proposed circuit contributes to millimeter-wave receivers for stable performances in radar applications.

Design of a Distributed Mixer Using Dual-Gate MESFET's (Dual-Gate MESFET를 이용한 분포형 주파수 혼합기의 설계)

  • Oh, Yang-Hyun;An, Jeong-Sig;Kim, Han-Suk;Lee, Jong-Arc
    • Journal of IKEEE
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    • v.2 no.1 s.2
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    • pp.15-23
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    • 1998
  • In this paper, distributed mixer is studied at microwave frequency. The circuit of distributed mixer composed of gate 1,2, drain transmission lines, matching circuits in input and output terminal, DGFET's. For impedance matching of input and output port at higher frequency, image impedance concept is introduced. In distributed mixer, a DGFET's impedances are absorbed by artificial transmission line, this type of mixer can get a very broadband characteristics compared to that of current systems. A RF/LO signal is applied to each gate input port, and are excited the drain transmission line through transcondutance of the DGFET's. The output signals from each drain port of DGFET's added in same phases. We designed and frabricated the distributed mixer, and a conversion gain, noise figure, bandwidth, LO/RF isolation of the mixer are shown through computer simulation and experimentation.

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