• Journal of electromagnetic engineering and science
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• 제10권1호
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• pp.25-27
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• 2010

This paper presents a gain and phase mismatch calibration technique for an image-reject RF receiver. The gain mismatch is calibrated by directly measuring the output signal amplitudes of two signal paths. The phase mismatch is calibrated by measuring the output amplitude of the final IF output at the image band. The calibration of the gain and phase mismatch is performed at power-up, and the normal operation of the RF receiver does not interfere with the mismatch calibration circuit. To verify the proposed technique, a 2.4-GHz Weaver image-reject receiver with the gain and phase mismatch calibration circuit is implemented in a 0.18-${\mu}m$ CMOS technology. The overall receiver achieves a voltage gain of 45 dB and a noise figure of 4.8 dB. The image rejection ratio(IRR) is improved from 31 dB to 59.76 dB even with 1 dB and $5^{\circ}$ mismatch in gain and phase, respectively.

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.769-780
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• 2018

This paper presents an analysis of the power gain under partial shading conditions (PSC) when the partial shade loss is being compensated in photovoltaic(PV) system. To analyze the power gain, our study divides the mismatch loss into partial shade loss and operating point loss. Partial shade loss is defined as the power difference between a normal string and a partially shaded string at the maximum power point (MPP). Operating point loss is defined as the power loss due to the operating point shift while following the MPP of the PV array. Partial shading in a PV system affects the maximum power point tracking (MPPT) control by creating multiple MPPs, which causes mismatch losses. Several MPPT algorithms have been suggested to solve the multiple MPP problems. Among these, mismatch compensation algorithms require additional power to compensate for the mismatch loss; however, these algorithms do not consider the gain or loss between the input power required for compensation and the increased output power obtained after compensation. This paper analyzes the power gain resulting from the partial shade loss compensation under PSC, using the V-P curve of the PV system, and verifies that power gain existence by simulation and experiment.

• 드라이브 ㆍ 컨트롤
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• 제13권1호
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• pp.34-42
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• 2016

This study studied how the clearance, overlap and mismatch errors of spool-sleeve affect the static pressure characteristics of a servo valve. A computer simulation model was established as a direct acting servo valve and a series of simulations was conducted for various values of clearance, overlap and mismatch errors. Pressure gain decreased as the clearance increased. The overlap also affects the pressure gain and was similar to the effect of clearance. Asymmetry of the pressure plot got worse and worse as the mismatch error increased.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 춘계학술대회 논문집
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• pp.127-128
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• 2010

• ETRI Journal
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• 제26권5호
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• pp.501-504
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• 2004

This paper presents a simple gain/phase blind compensation algorithm with an automatic gain control (AGC) function for the adoption of the AGC function and compensation for gain/phase imbalances in quadrature phase shift keying (QPSK) direct conversion receivers (DCRs). The AGC function is interactively operated with the compensation algorithm for gain/phase imbalances. By detecting the gain sum and difference values between the I-channel and Q-channel, the combined AGC and gain imbalance compensation algorithm provides a simpler DCR architecture.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.96-100
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• 2015

Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ${\sum}{\Delta}$ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at $10^{-6}$ BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

• 한국전자파학회논문지
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• 제24권3호
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• pp.278-285
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• 2013

본 논문에서는 상용 65 n CMOS 공정을 이용하여 100~110 GHz에서 동작하는 저잡음 증폭기와 커플러를 구현하였다. 제작된 LNA는 3단 공통 소스 FET로 구성되었다. 단위 공통 소스 셀의 높은 이득 특성을 얻기 위해 이를 고려한 레이아웃을 하였다. 또한, 저잡음 특성과 충분한 이득을 얻기 위해 성능을 최적화시켰다. 커플러는 CMOS 공정의 multimetal을 이용한 broadside 커플러로 구성하였다. Density rule을 만족시키기 위한 metal strip을 사용해 이에 의한 영향을 고려해 커플러 동작이 가능하도록 설계하였다. 제작된 저잡음 증폭기의 측정 결과, 100 GHz에서 5.64 dB, 110 GHz에서 6.39 dB의 이득과 10 % 이상의 3-dB 대역폭, 11.66 dB의 잡음 지수를 얻었다. 커플러는 100~110 GHz 대역에서 2~3 dB의 삽입 손실, 1 dB 이하의 magnitude mismatch와 $5^{\circ}$ 이하의 phase mismatch를 얻었다.

• 대한전자공학회논문지
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• 제23권5호
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• pp.597-604
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• 1986

This paper describes various mismatch phenomena in differential pulse code modulation (DPCM) coding, such as the mismatch effects of probability density functin(pdf), signal variance, and correlation. At a high transmission rate(i.e., above 32 kbits/s), the performance of DPCM can be improved by matching the pdf shape between the input signal and the quantizer. However, the same gain cannot be obtained at a lower transmission rate. Also, it is shown that the gamma quantizer is realtively robust to the variation of pdf shaper and signal variance. Moreover, as the transmission rate increases, the performance of DPCM for the input signal with large variance is worse than that of DPCM for the signal with small variance due to the increase of overload noise. According to our simuladiton results, the mismatch effects of pdf shape and variance appear to yield more degradatin than that of correlation in a DPCM system.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2007년도 학술대회
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• pp.423-426
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• 2007

An active Balun is designed for RFID reader at 2.45GHz. The Balun is integrated inside the receiver, then the LNA and mixer can be connected. The unbalanced LNA output signal is transformed to a balanced signal at the input mixer The RF mixer and LO mixer, by using this balun. The Balun provided a balanced signal with two output stage, gain mismatch is 0.116dB. The phase show a good behavior with $163.918^{\circ}$,$-16.609^{\circ}$. The phase mismatch is about $0.527^{\circ}$. The tight difference between the gain and phase on each brancd, is because of the used capacitor and integrated inductor and the other parasitic element inside the balun.

• IEIE Transactions on Smart Processing and Computing
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• 제3권4호
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.