• Journal of Mechanical Science and Technology
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• 제16권2호
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• pp.155-164
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• 2002

The power steering system for vehicles is becoming essential for supporting the steering efforts of the drivers, especially for the parking lot maneuver Although hydraulic power steering has been widely used for years, its efficiency is not high enough. The problems associated with a hydraulic howe. steering system can be solved by a motor driven power steering (MDPS) system. In this study, a dynamic model and a control algorithm for the ball screw type of MDPS system have been derived and analyzed by using the method of discrete modeling technology. To improve steering feel and power steering characteristics, two derivative gains are added to the conventional power boosting control algorithm. Through simulations, the effects of the control gain on the steering angle gain were verified in the frequency domain. The steering returnability and steering torque phase lag in on-center handling test were also evaluated in the time domain.

• 한국자동차공학회논문집
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• 제8권1호
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• pp.124-134
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• 2000

The power wteering system for automobiles is becoming core popular for supporting steering efforts of the drivers, especially for a parking lot maneuver. Though hydraulic power steering has been widely used for a long time, the efficiency of that is not high enough. The motor driven power steering system can solve the problems associated with the hydraulic power steering system. In this study, dynamic model and control algorithm of the ball screw type of MDPS systenem have been derived and analysed by using the method of discrete modeling technology. To improve steering feel and power steering characteristics, the additional scheme is proposed to the conventional power boosting control algorithm. Through simulations, control gain effects to the steering angle gain in the frequency domain were verified. The steering returnability and steering torque phase lag in on-center handing test were performed also.

• 대한의용생체공학회:의공학회지
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• 제28권2호
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• pp.199-204
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• 2007

In digital radiography, to improve the contrast of digital radiography image, the multi-scale nonlinear amplification algorithm based on unsharp masking is one of the major image enhancement algorithms. In this paper, we used the Laplacian pyramid to decompose a digital radiography(DR) image. In our simulation, the DR image was decomposed into seven layers and the coefficients of the each layer was amplified with nonlinear function. We also imported a noise containment algorithm to limit noise amplification. To enhance the contrast of image, we proposed a new adaptive non-linear gain amplification coefficients. As a result of having applied to some clinical data, a detail visibility was improved significantly without unacceptable noise boosting. Images that acquired with the proposed adaptive non-linear gain coefficients have shown superior quality to those that applied similar gain control method and expected to be accepted in the clinical applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.405-410
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• 2012

This paper presents an inductorless 8-Gb/s adaptive passive equalizer with low-power consumption and small chip area. The equalizer has a tunable RC filter which provides high-frequency gain boosting and a limiting amplifier that restores the signal level from the filter output. It also includes a feedback loop which automatically adjusts the filter gain for the optimal frequency response. The equalizer fabricated in $0.18-{\mu}m$ CMOS technology can successfully equalize 8-Gb/s data transmitted through up to 50-cm FR4 PCB channels. It consumes 6.75 mW from 1.8-V supply voltage and occupies $0.021mm^2$ of chip area.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.299-301
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• 2014

본 논문에서는 직류 오프셋 (DC-offset) 제거 기능을 가진 저 전력 자동 이득 조절 증폭기 (PGA, Programmable Gain Amplifier)를 제안한다. 이러한 회로는 직류 오프셋 문제점을 해결하기 위해 기존의 gm-boosting 증폭기를 변형한 디지털 이득 제어 방식으로 설계되어 있기 때문에 우수한 선형성을 가진다. 또한 특수 목적에 맞도록 그 이득을 6dB에서 60dB까지 7단계로 조절 가능하며, 밀러효과를 이용한 AC-coupling 방식으로 큰 값의 유동적인 커패시터와 저항을 구현하여 직류 오프셋을 제거한다. 제안한 PGA는 기존 회로에 비해 0.2dB 보다 작은 이득오차와 0.47mW의 낮은 소비전력 특성을 보였다.

• 정보처리학회논문지A
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• 제12A권6호
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• pp.531-538
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• 2005

고성능 VLSI 아날로그 정보처리시스템(AIPS)에서 고 이득 Op-Amp는 기본적 정보처리소자이다. 증폭기는 시스템 내 피드백루프에 사용시 안정도와 정확도를 얻기 위하여 고 이득이 요구된다. 1단의 증폭으로 이득이 충분하지 않을 경우 이득 부스팅 또는 추가적인 이득단이 필요하다. 본 논문에서 부 저항소자를 사용할 경우 이득이 개선되며 1단으로 고 이득을 손쉽게 얻을 수 있음을 보였다. 기존의 방법에 비교하여 본 연구에 제안된 방법은 전 출력 스윙, 적은 회로면적과 전력소비, 그리고 여러 구조의 증폭기에 적용가능 하다는 잇점을 지니고 있다. 부 저항소자는 Op-Amp에 사용될 경우 (+)와 (-) 차동출력 사이에 설치되어 증폭기 출력저항을 상쇄한다. 부 저항소자를 교차 연결된 CMOS 인버터의 형태로 구현할 경우 간단한 구조로서 40 dB 보다 더 큰 이득개선을 손쉽게 얻을 수 있음을 HSPICE 시뮬레이션을 통하여 확인하였다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2019년도 추계학술발표대회
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• pp.585-588
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• 2019

Predictions of Energy Consumption for Industries gain an important place in energy management and control system, as there are dynamic and seasonal changes in the demand and supply of energy. This paper presents and discusses the predictive models for energy consumption of the steel industry. Data used includes lagging and leading current reactive power, lagging and leading current power factor, carbon dioxide (tCO2) emission and load type. In the test set, four statistical models are trained and evaluated: (a) Linear regression (LR), (b) Support Vector Machine with radial kernel (SVM RBF), (c) Gradient Boosting Machine (GBM), (d) random forest (RF). Root Mean Squared Error (RMSE), Mean Absolute Error (MAE) and Mean Absolute Percentage Error (MAPE) are used to measure the prediction efficiency of regression designs. When using all the predictors, the best model RF can provide RMSE value 7.33 in the test set.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.309-315
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• 2010

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1484-1494
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• 2017

We present a two-stage inverter with high step-up conversion ratio engaging modified finite-set Model Predictive Control (MPC) for utility-integrated photovoltaic (PV) applications. The anticipated arrangement is fit for low power PV uses, the calculated efficiency at 150 W input power and 19 times boosting ratio was around 94%. The suggested high-gain dc-dc converter based on Cockcroft-Walton multiplier constitutes the first-stage of the offered structure, due to its high step-up ability. It can boost the input voltage up to 20 times. The 3S current-source inverter constitutes the second-stage. The 3S current-source inverter hires three semiconductor switches, in which one is functioning at high-frequency and the others are operating at fundamental-frequency. The high-switching pulses are varied in the procedure of unidirectional sine-wave to engender a current coordinated with the utility-voltage. The unidirectional current is shaped into alternating current by the synchronized push-pull configuration. The MPC process are intended to control the scheme and achieve the subsequent tasks, take out the Maximum Power (MP) from the PV, step-up the PV voltage, and introduces low current with low Total Harmonic Distortion (THD) and with unity power factor with the grid voltage.