• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.569-572
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• 2014

본 논문에서는 MEMS 용량형 센서를 위한 CMOS 스위치드-커패시터 인터페이스 회로를 설계하였다. 설계된 회로는 커패시턴스-전압 변환기(CVC), 2차 스위치드 커패시터 ${\Sigma}{\Delta}$ 변조기 및 비교기로 구성되어있다. 또한 일정한 바이어스를 공급해주는 바이어스 회로를 추가하였다. 전체적인 회로의 저주파 잡음과 오프셋을 감소시키기 위하여 Correlated-Double-Sampling(CDS) 기법과 Chopper-Stabilization(CHS) 기법을 적용하였다. 설계 결과 CVC는 20.53mV/fF의 민감도와 0.036%의 비선형성특성을 보였으며, ${\Sigma}{\Delta}$ 변조기는 입력전압 진폭이 100mV가 증가할 때, 출력의 듀티 싸이클은 약 5%씩 증가하였다. 전체회로의 선형성 에러는 0.23% 이하이며, 전류소모는 0.73mA이다. 제안된 회로는 0.35um CMOS 공정을 이용하여 설계되었으며, 입력전압은 3.3V이다. 설계된 칩의 크기는 패드를 포함하여 $1117um{\times}983um$ 이다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.68-69
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• 2011

Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the peak current controlled (PCC) buck converter with a wide input voltage. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.284-288
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• 2005

This paper proposes the direct detection method of phase angle for the power source, which is based on the PLL method. The proposed method using a bidirectional photo-coupler is used to directly detect the zero crossing of phase voltage and calculate the angular frequency in the controller based on a M/T algorithm. Through the method, the additional installation space in the traditional method using a potential transformer can be minimized and it can be easy to design. The paper presents straightforward schematic circuits, design and experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.988-991
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• 1992

A new zero voltage switching PWN converter family is presented by using a new ZVS PWN module (ZPM) with a saturable inductor which prevents diode junction capacitors and a commutation inductor from resonating. The new converters show almost all characteristics of the conventional PWN converters. A boost ZVS PWN converter is applied to a power factor correction circuit. It operates on an continuous conduction mode. Experimental results for output power of 1kW are presented.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2007년도 추계학술대회 논문집
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• pp.1438-1444
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• 2007

Standard Gate Turn Off (GTO) Thyristor drive technology results in inhomogeneous turn-on and turn-off transients which in turn needs costly dv/dt and di/dt snubber circuits. Added to this GTO is bulky in size, needs external cooling, slower switching time etc. The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO technology. Indian Railway has developed first IGBT based traction converter and was commissioned in November 2006. Some of the supremacy of IGBT are smaller in size, no external cooling is required, built in power supply which enhances reliability, lower switching losses which leads to higher efficiency, reduced gate drive, high frequency operation in real time etc. These advantages are highlighted along with IGBT Traction system in operation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1960-1962
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• 1998

Reference/modulating waveform continuity is not a necessary condition for the implementation of switching patterns for three-phase pulse-width modulated(PWM) converters. This is based on the fact that the converter phase-voltages do not need to be sinusoidal and switching pattern discontinuities do not degrade the quality of output/input voltage/current waveforms by introducing low-order harmonics if certain parameters are optimized. This paper introduces the selected harmonic elimination to reduce the switching frequency and low-order harmonics compared with continuous PWM techniques and some discontinues switching patterns for PWM converter.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.68-71
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• 2021

In this paper, GaN-SBD devices with excellent breakdown voltage and frequency characteristics for use in high-power microwave wireless power transmission has been modeled for PSpice circuit simulation. The RF-DC conversion circuits were simulated and compared with a commercial Si-SBD device. Although the modeled GaN-SBD devices had lower RF-DC conversion efficiency compared to Si-SBD at 2.4 and 5.8 GHz, it was confirmed through PSpice circuit simulations that they can be used sufficiently according to the required application circuit in a high power situation.

• ETRI Journal
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• 제30권4호
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

• Journal of Power Electronics
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• 제19권1호
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• pp.119-133
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• 2019

Although the dual modulation wave method can solve the low-frequency neutral point potential (NPP) fluctuation problem for three-level neutral point clamped converters, it also increases the switching frequency and limits the zero-sequence voltage. That makes it harmful when dealing with the NPP drift problem if the converter suffers from a long dead time or asymmetric loads. By introducing two degrees of freedom (2-DOF), an NPP control based on a search optimization method can demonstrate its ability to cope with the above mentioned two types of NPP problems. However, the amount of calculations for obtaining an optimal 2-DOF is so large that the method cannot be applied to certain industrial applications with an inexpensive digital signal processor. In this paper, a novel optimal 2-DOF-based NPP control is proposed. The relationships between the NPP and the 2-DOF are analyzed and a method for directly determining the optimal 2-DOF is also discussed. Using a direct calculation method, the amount of calculations is significantly reduced. In addition, the proposed method is able to maintain the strongest control ability for the two types of NPP problems. Finally, some experimental results are given to confirm the validity and feasibility of the proposed method.

• 한국통신학회논문지
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• 제25권1B호
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• pp.183-192
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• 2000

본 논문에서는 전류펌핑 알고리즘을 이용한 클락 동기용 3.3V 단일 공급 전압하에서 3-250MHz 입력 록킹 범위를 갖는 2중 루프 구조의 CMOS PLL 회로를 설계하였다. 본 논문은 전압 제어 발진기 회로의 전압대 주파수의 선형성을 향상시키기 위한 전류펌핑 알고리즘을 이용한 PLL 구조를 제안한다. 설계된 전압 제어 발진기 회로는 75.8MHz-1GHz 의 넓은 주파수 범위에서 높은 성형성을 가지고 동작한다. 또한, 록킹 되었을 때 루프 필터 회로를 포함한 저하 펌프 회로의 전압 변동 현상을 막는 위상 주파수 검출기 회로를 설계하였다. 0.6$\mu\textrm{m}$ N-well single-poly triple metal CMOS 공정을 사용하여 모이 실험 한 결과, 125MHz의 입력 주파수를 갖고 1GHz의 동작 주파수에서 3.5$\mu\textrm{s}$의 록킹 시간과 92mW의 전력 소모를 나타내었다. 측정 결과 V-I 컨버터 회로를 포함한 VCO 회로의 위상 잡음은 100kHz의 옵셋 주파수에서 -100.3dBc/Hz를 나타내었다.