• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.257-260
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• 2002

In this paper, the circuit of AC Choppers for $CO_2$laser Power Supply are proposed and investigated. IGBT-controlled ac voltage regulators, operating at high frequency chopping mode. Chopping-to-supply duty ratio plays an important role in terms of laser output. Laser input energy is varied by controlling the leakage transfomer used with the proposed system. This improved circuit employs a 3 electrode-type and Ring Blower. This improved circuit system has many advantages compared with the conventional SMPS such as simple design requirment, easy implementation, high reliability, low switching loss, and consequently high efficiency. As a result, the maximun output was 16W at duty-ratio of 92%, total gas mixture of $CO_2$: $N_2$: He = 1 : 9 : 15, total pressure of 15torr.

• Journal of Power Electronics
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• v.19 no.1
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• pp.1-10
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• 2019

Current imbalance is the main factor affecting the lifespan of light-emitting diode (LED) lighting systems and is generally solved by active or passive approaches. Given many new lighting applications, independent control is particularly important in achieving different levels of luminance. Existing passive and active approaches have their own limitations in current sharing and independent control, which bring new challenges to the design of LED drivers. In this work, a multichannel resonant converter based on switched-capacitor control (SCC) is proposed for solving this challenge. In the resonant network of the upper and lower half-bridges, SCC is used instead of fixed capacitance. Then, the individual current of the LED array is obtained through regulation of the effective capacitance of the SCC under a fixed switching frequency. In this manner, the complexity of the control unit of the circuit and the precision of the multichannel outputs are further improved. Finally, the superior performance of the proposed LED driver is verified by simulations and a 4-channel experimental prototype with a rated output power of 20 W.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.369-370
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• 2020

본 논문에서는 전기자동차용 양방향 배터리 충전장치에 사용되는 CHFL(Cycloconverter-type High Frequency Link) 컨버터에서 발생하는 고전압 스파이크 저감을 위한 스위칭 방법을 제안한다. CHFL 컨버터는 양극성 고주파 파형 정류시 LC 필터의 인덕터와 변압기의 누설 인덕터에 저장된 에너지로 인해 고전압 스파이크가 발생하게 된다. 제안된 스위칭 방법은 환류 구간을 통해 저장된 에너지를 회생시킴으로서 고전압 스파이크 문제를 해결할 수 있다. 제안된 스위칭 방법의 성능은 MATLAB/ Simulink 시뮬레이션을 통해 검증하였다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.261-261
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• 2007

Wearable and ubiquitous micro systems will be greatly growing and their related devices should be self-powered in order to avoid the replacement of finite power sources, for example, by scavenging energy from the environment. With ever reducing power requirements of both analog and digital circuits, power scavenging approaches are becoming increasingly realistic. One approach is to drive an electromechanical converter from ambient motion or vibration. Vibration-driven generators based on electromagnetic, electrostatic and piezoelectric technologies have been demonstrated. Among various generator types proposed so far, piezoelectric generator possesses considerable potential in micro system. To overcome low mechanical-to- electric energy conversion, the piezoelectric device should activate in resonance mode in response to external vibration. Normally, the external vibration excretes at low frequency ranging 0.1 to 200 Hz, whereas the resonant frequencies of the devices are fixed as constant. Therefore, keeping their resonant mode in varying external vibration can be one of important points in enhancing the conversion efficiency. We investigated the possibility of use of multi-bender type piezoelectric devices. To match the external vibration frequency with the device resonant frequency, the various devices with different resonant frequency were chosen. Under an external vibration acceleration of 0.1G at 120 Hz, the device exhibited a peak-to-peak voltage of 2.8 V and a power of 0.5 mw in resonance mode.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1110-1121
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• 2016

The mathematical model of a three phase PWM converter under the stationary αβ reference frame is deduced and constructed based on a Proportional-Resonant (PR) regulator, which can replace trigonometric function calculation, Park transformation, real-time detection of a Phase Locked Loop and feed-forward decoupling with the proposed accurate calculation of the inductance voltage vector. To avoid the parallel resonance of the LCL topology, the active damping method of the proportional capacitor-current feedback is employed. As to current vector error elimination, an optimized PR controller of the inner current loop is proposed with the zero-pole matching (ZPM) and cancellation method to configure the regulator. The impacts on system's characteristics and stability margin caused by the PR controller and control parameter variations in the inner-current loop are analyzed, and the correlations among active damping feedback coefficient, sampling and transport delay, and system robustness have been established. An equivalent model of the inner current loop is studied via the pole-zero locus along with the pole placement method and frequency response characteristics. Then, the parameter values of the control system are chosen according to their decisive roles and performance indicators. Finally, simulation and experimental results obtained while adopting the proposed method illustrated its feasibility and effectiveness, and the inner current loop achieved zero static error tracking with a good dynamic response and steady-state performance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.5
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• pp.10-24
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• 2007

In the dissertation, a power conversion system for fuel cell is composed of a PWM inverter with LC filter in order to convert fuel cell voltage to a single phase 220[V]. In addition, new insulated DC-DC converters are proposed in order that fuel cell voltage is boosted to 380[V]. In this paper, it requires smaller components than existing converters, which makes easy control. The proposed DC-DC converter controls output power by the adjustment of phase-shift width using switch $S_5\;and\;S_6$ in the secondary switch which provides 93-97[%] efficiency in the wide range of output voltage. Fuel cell simulator is implemented to show similar output characteristics to actual fuel cell. Appropriate dead time td enables soft switching to the range where the peak value of excitation current in a high frequency transformer is in accordance with current in the primary circuit. Moreover, appropriate setting to serial inductance La reduces communication loss arisen at light-load generator and serge voltage arisen at a secondary switch and serial diode. Finally, TMS320C31 board and EPLD using PWM switching technique to act a single phase full-bridge inverter which is planed to make alternating current suitable for household

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.