• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.68-69
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• 2011

Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the peak current controlled (PCC) buck converter with a wide input voltage. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.284-288
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• 2005

This paper proposes the direct detection method of phase angle for the power source, which is based on the PLL method. The proposed method using a bidirectional photo-coupler is used to directly detect the zero crossing of phase voltage and calculate the angular frequency in the controller based on a M/T algorithm. Through the method, the additional installation space in the traditional method using a potential transformer can be minimized and it can be easy to design. The paper presents straightforward schematic circuits, design and experimental results.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.988-991
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• 1992

A new zero voltage switching PWN converter family is presented by using a new ZVS PWN module (ZPM) with a saturable inductor which prevents diode junction capacitors and a commutation inductor from resonating. The new converters show almost all characteristics of the conventional PWN converters. A boost ZVS PWN converter is applied to a power factor correction circuit. It operates on an continuous conduction mode. Experimental results for output power of 1kW are presented.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1438-1444
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• 2007

Standard Gate Turn Off (GTO) Thyristor drive technology results in inhomogeneous turn-on and turn-off transients which in turn needs costly dv/dt and di/dt snubber circuits. Added to this GTO is bulky in size, needs external cooling, slower switching time etc. The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO technology. Indian Railway has developed first IGBT based traction converter and was commissioned in November 2006. Some of the supremacy of IGBT are smaller in size, no external cooling is required, built in power supply which enhances reliability, lower switching losses which leads to higher efficiency, reduced gate drive, high frequency operation in real time etc. These advantages are highlighted along with IGBT Traction system in operation.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1960-1962
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• 1998

Reference/modulating waveform continuity is not a necessary condition for the implementation of switching patterns for three-phase pulse-width modulated(PWM) converters. This is based on the fact that the converter phase-voltages do not need to be sinusoidal and switching pattern discontinuities do not degrade the quality of output/input voltage/current waveforms by introducing low-order harmonics if certain parameters are optimized. This paper introduces the selected harmonic elimination to reduce the switching frequency and low-order harmonics compared with continuous PWM techniques and some discontinues switching patterns for PWM converter.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.68-71
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• 2021

In this paper, GaN-SBD devices with excellent breakdown voltage and frequency characteristics for use in high-power microwave wireless power transmission has been modeled for PSpice circuit simulation. The RF-DC conversion circuits were simulated and compared with a commercial Si-SBD device. Although the modeled GaN-SBD devices had lower RF-DC conversion efficiency compared to Si-SBD at 2.4 and 5.8 GHz, it was confirmed through PSpice circuit simulations that they can be used sufficiently according to the required application circuit in a high power situation.

• ETRI Journal
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• v.30 no.4
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

• Journal of Power Electronics
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• v.19 no.1
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• pp.119-133
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• 2019

Although the dual modulation wave method can solve the low-frequency neutral point potential (NPP) fluctuation problem for three-level neutral point clamped converters, it also increases the switching frequency and limits the zero-sequence voltage. That makes it harmful when dealing with the NPP drift problem if the converter suffers from a long dead time or asymmetric loads. By introducing two degrees of freedom (2-DOF), an NPP control based on a search optimization method can demonstrate its ability to cope with the above mentioned two types of NPP problems. However, the amount of calculations for obtaining an optimal 2-DOF is so large that the method cannot be applied to certain industrial applications with an inexpensive digital signal processor. In this paper, a novel optimal 2-DOF-based NPP control is proposed. The relationships between the NPP and the 2-DOF are analyzed and a method for directly determining the optimal 2-DOF is also discussed. Using a direct calculation method, the amount of calculations is significantly reduced. In addition, the proposed method is able to maintain the strongest control ability for the two types of NPP problems. Finally, some experimental results are given to confirm the validity and feasibility of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.