• International journal of advanced smart convergence
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• v.9 no.1
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• pp.172-176
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• 2020

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of -122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.155-159
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• 2003

This paper presents fully integrated 5 GHz band low phase noise LC tank VCO. The implemented VCO is tuned by integrated PN diode and tuning rage is $5.01{\sim}5.30$ GHz under $0{\sim}3 V$ control voltage. For good phase noise performance, LC filtering technique, common in Si CMOS process, is used, and to prevent degradation of phase noise performance by collector shot-noise and to reduce power dissipation the HBT is biased at low collector current density bias point. The measured phase noise is -87.8 dBc/Hz at 100 kHz offset frequency and -111.4 dBc/Hz at 1 MHz offset frequency which is good performance. Moreover phase noise is improved by roughly 5 dEc by LC filter. It is the first experimental result in InGaP/GaAs HBT process. The figure of merit of the fabricated VCO with LC filter is -172.1 dBc/Hz. It is the best result among 5 GHz InGaP HBT VCOs. Moreover this work shows lower DC power consumption, higher output power and more fixed output power compared with previous 4, 5 GHz band InGaP HBT VCOs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.77-80
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• 2008

In this paper, low phase noise VCO using novel compact microstrip spiral resonator is proposed. A spiral resonator has super compact dimension, low insertion losses in the passband and high level of rejection in the stopband with sharp cutoff and a large coupling coefficient value, which makes a high Q value, and has reduced the phase noise. To increase the tuning range of VCO, varactor diode has been connected at the tunable negative resistance in VCO. This VCO has presented the oscillation frequency of $5.686{\sim}5.841GHz$, harmonics -29.83 dBc and phase noise of $-115.16{\sim}-115.17dBc/Hz$ at the offset frequency of 100 KHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.964-969
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• 2007

A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.35-38
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• 2010

A fully integrated parallel-coupled 6-GHz quadrature voltage-controlled oscillator (QVCO) has been designed. The symmetrical parallel-coupled quadrature VCO is implemented using 0.13-${\mu}m$ CMOS process. The measured phase noise is -101.05 dBc/Hz at an offset frequency of 1 MHz. The tuning range of 710 MHz is achieved with a control voltage ranging from 0.3 to 1.4 V. The average output phase error is about $1.26^{\circ}$ including cables and connectors. The QVCO dissipates 10 mA including buffer from the 1.5 V supply voltage. The output characteristic of the differential injection-locked frequency divider (DILFD), which has similar topology to the QVCO, is presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.6
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• pp.691-699
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• 2012

In this paper, we present a Vt-DRO with a low phase noise, which is achieved by improving the coupling structure between the dielectric resonator and microstrip line. The Vt-DRO is a closed-loop type and is composed of 3 blocks; dielectric resonator, phase shifter, and amplifier. We propose a mathematical estimation method of phase noise, using the group delay of the resonator. By modifying the coupling structure between the dielectric resonator and microstrip line, we achieved a group delay of 53 nsec. For convenience of measurement, wafer probes were inserted at each stage to measure the S-parameters of each block. The measured S-parameter of the Vt-DRO satisfies the open-loop oscillation condition. The Vt-DRO was implemented by connecting the input and output of the designed open-loop to form a closed-loop. As a result, the phase noise of the Vt-DRO was measured as -132.7 dBc/Hz(@ 100 kHz offset frequency), which approximates the predicted result at the center frequency of 5.3 GHz. The tuning-range of the Vt-DRO is about 5 MHz for tuning voltage of 0~10 V and the power is 4.5 dBm. PFTN-FOM is -31 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.