• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.586-591
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• 2000

In this paper, a PLHRO(Phase Locked Hair-pin Resonator Oscillator) for K-band is designed with the feedback property of PLL(Phase Locked Loop) using a new tuning mechanism. The proposed PLHRO generates the output power of -0.6 dBm at 24.42 GHz, and has the phase noise of -86.6 dBc/Hz at 100 KHz and -76.5 dBc/Hz at 10KHz offset from carrier frequency, and has suppression characteristics of -23 dBc and spurious noise of -65 dBc. Buffered 24.42 GHz PLHRO generates the output power of 5.6 dBm at 24.42 GHz and has the of a phase noise of -77.34 dBc/Hz at 100 KHz and -72 dBc/Hz at 100 KHz offset from carrier frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.41-46
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• 2012

A quadrature voltage controlled oscillator(QVCO) for X-band is presented in this paper. The QVCO has fabricated in Charted $0.13{\mu}m$ CMOS process. The QVCO consists of two cross-coupled differential VCO and two differential buffers. The QVCO is controlled by 4 bit of capacitor bank and control voltage of varactor. To have a linear quality factor of varactors, voltage biases of varactors are difference. The QVCO generates frequency tuning range from 6.591 GHz to 8.012 GHz. The phase noise is -101.04 dBc/Hz at 1MHz Offset when output frequency is 7.150 GHz. The supply voltage is 1.5 V and core current 6.5-8.5 mA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.213-218
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• 2007

In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.971-978
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• 2005

In this paper, we design and fabricate a VCO(Voltage Controlled Oscillator) for radar detector of X/K/Ka band using frequency multiplier. The existing VCO operated in radar detector have many Problems such as narrow bandwidth, slow frequency variable rate, unstable of production due to high frequency. So we design and fabricate a VCO improved such problems using frequency multiplier. As a result of measure, investigated frequency multiple VCO show its output power 3.64 dBm at multiplied operating frequency 11.27 GHz and have wide frequency tuning range of 660 MHz by controlled voltage 0V to 4.50 V applied diode. And also its phase noise is -104.0 dEc at 1 MHz offset frequency so we obtain suitable performance for commercial use.

• Journal of electromagnetic engineering and science
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• v.6 no.1
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• pp.30-35
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• 2006

This paper describes fully integrated low phase noise MMIC voltage controlled oscillators(VCOs). The Asymmetrical Inductance Tank VCO(AIT-VCO), which optimize the shortcoming of the previous tank's inductance optimization approach, has lower phase noise performance due to achieving higher equivalent parallel resistance and Q value of the tank. This VCO features an output power signal in the range of - 11.53 dBm and a tuning range of 261 MHz or 15.2 % of its operating frequency. This VCO exhibits a phase noise of - 117.3 dBc/Hz at a frequency offset of 100 kHz from carrier. A phase noise reduction of 15 dB was achieved relative to only one spiral inductor. The AIT-VCO achieved low very low figure of merit of -184.6 dBc/Hz. The die area, including buffers and bond pads, is $0.9{\times}0.9mm^2$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.12
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• pp.16-21
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• 2007

In this paper, the dual-band voltage-controled oscillator (VCO) using the composite right/left-handed (CRLH) transmission line (TL) and the tunable negative resistance based on the fin diode is presented. It is demonstrated that the CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the phase slope of the CRLH TL, and the frequency ratio of the two operating frequencies can be a non-integer. Each frequency band of VCO has to operate independently, so we have used the tunable negative resistance based on the pin diode. When the forward bias has been into the pin diode, the phase noise of VCO is $-108.34\sim-106.67$ dBc/Hz @ 100 kHz in the tuning range, $2.423\sim2.597$ GHz, whereas when the reverse bias has been fed into the pin diode, that of VCO is $-114.16\sim-113.33$ dBc/Hz @ 100 kHz in the tuning range, $5.137\sim5.354$ GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1125-1134
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• 2011

In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.