• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.131-137
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• 2014

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of $1385{\times}835{\mu}m^2$.

• 한국전자파학회논문지
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• 제20권11호
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• pp.1178-1185
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• 2009

본 논문은 2.5 MHz 간격으로 광대역 주파수를 발생하며 응답 시간이 400 nsec 이하인 초고속 이산(discrete) 주파수 합성기를 제안한다. 제안한 주파수 합성기는 고정 주파수 위상 제어 루프(PLL)와 주파수 분배기를 이용해 16개의 기준 신호를 생성하고, 이들을 선택하여 주파수 혼합하는 방식으로 710~1,610 MHz내에서 2.5 MHz 간격의 이산 주파수 신호를 고속으로 생성한다. 제작된 주파수 합성기의 주파수 천이 응답 시간은 평균 350 nsec, 고조파를 비롯한 모든 불요파 신호는 -60 dBc 이하, 위상 잡음 특성은 -94 dBc/Hz @100 Hz, 출력 세기는 평균 21.5 dBm, 평탄도는 2.65 dB 이하로 측정되었다. 또한 주파수 천이 응답 속도를 측정하는 새로운 기법의 측정 방법이 제안되었다.