• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.131-137
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• 2014

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of $1385{\times}835{\mu}m^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1178-1185
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• 2009

In this paper, a wideband ultra-high speed & high purity discrete frequency synthesizer having minimum 2.5 MHz step size was proposed. To achieve fast and wideband operation, discrete frequencies were synthesized by mixing of 3 different pre-synthesized 16 frequencies made from fixed PLL and frequency dividers. Frequencies with discrete 2.5 MHz step were produced in 710~1,610 MHz. The measured hopping response time was 350 nsec average, output level was 21.5 dBm average with 2.65 dB flatness, spurious and harmonics level were suppressed below -60 dBc, and phase noise was -94 dBc/Hz@100 Hz. Also, a new measurement method for synthesizer response time was described.