• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.123-134
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• 2000

This paper addresses a new triangulation method for constructing surface model from a set of wire-frame contours. The most important problem of contour triangulation is the branching problem, and we provide a new solution for the double branching problem, which occurs frequently in real data. The multiple branching problem is treated as a set of double branchings and an algorithm based on contour merging is developed. Our double branching algorithm is based on partitioning of root contour by Toussiant's polygon triangulation algorithml[14]. Our double branching algorithm produces quite natural surface model even if the branch contours are very complicate in shape. We treat the multiple branching problem as a problem of coarse section sampling in z-direction, and provide a new multiple branching algorithm which iteratively merge a pair of branch contours using imaginary interpolating contours. Our method is a natural and systematic solution for the general branching problem of contour triangulation. The result shows that our method works well even though there are many complicated branches in the object.

• Journal of Korea Multimedia Society
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• v.17 no.10
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• pp.1189-1197
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• 2014

Recently, general purpose graphic processing units(GPUs) are being widely used in mobile embedded systems such as smart phone and tablet PCs. Because of architectural limitations of mobile GPGPUs, only a single program is allowed to occupy a GPU at a time in a non-preemptive way. As a result, it is difficult to meet performance requirements of applications such as frame rate or response time if applications running on a GPU are not scheduled properly. To tackle this difficulty, we propose to specify applications using synchronous data flow model of computation such that applications are formed with edges and nodes. Then nodes of applications are scheduled onto a GPU unlike conventional scheduling an application as a whole. This approach allows applications to share a GPU at a finer granularity, node (or task)-level, providing several benefits such as eliminating need for manually partitioning applications and better GPU utilization. Furthermore, any scheduling policy can be applied in response to the characteristics of applications.

• The Journal of the Korea Contents Association
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• v.12 no.8
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• pp.20-28
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• 2012

DVC(Distributed Video Coding) technique is a new paradigm, which is based on the Slepian-Wolf and Wyner-Ziv theorems. DVC offers not only flexible partitioning of the complexity between the encoder and decoder, but also robustness to channel errors due to intrinsic joint source-channel coding. Many conventional research works have been focused on the light video encoder and its rate-distortion performance improvement. However, in this paper, we propose a new DVC codec which is effectively applicable for error-prone environment. The proposed method adopts a quantiser without dead-zone and symmetric Gray code around zero value. Through computer simulations, the proposed method is evaluated by the bit errors position as well as the number of burst bit errors. Additionally, it is shown that the maximum and minimum transmission rate for the given application can be linearly determined by the number of bit errors.

• Journal of Broadcast Engineering
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• v.23 no.1
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• pp.115-125
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• 2018

This paper presents a fast partition decision framework for High Efficiency Video Coding (HEVC) Screen Content Coding (SCC) based on machine learning. Currently, the HEVC performs quad-tree block partitioning process to achieve optimal coding efficiency. Since this process requires a high computational complexity of the encoding device, the fast encoding process has been studied as determining the block structure early. However, in the case of the screen content video coding, it is difficult to apply the conventional early partition decision method because it shows different partition characteristics from natural content. The proposed method solves the problem by classifying the screen content blocks after partition decision, and it shows an increase of 3.11% BD-BR and 42% time reduction compared to the SCC common test condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.