• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.1
• /
• pp.41-48
• /
• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Journal of applied mathematics & informatics
• /
• v.25 no.1_2
• /
• pp.339-344
• /
• 2007

The relationships between binding number and fractional edge (vertex)-deletability or fractional k-extendability of graphs are studied. Furthermore, we show that the result about fractional vertex-deletability are best possible.

• Journal of IKEEE
• /
• v.3 no.1 s.4
• /
• pp.39-49
• /
• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Journal of the Korean Mathematical Society
• /
• v.53 no.4
• /
• pp.929-967
• /
• 2016

Let p(t, x) be the fundamental solution to the problem $${\partial}^{\alpha}_tu=-(-{\Delta})^{\beta}u,\;{\alpha}{\in}(0,2),\;{\beta}{\in}(0,{\infty})$$. If ${\alpha},{\beta}{\in}(0,1)$, then the kernel p(t, x) becomes the transition density of a Levy process delayed by an inverse subordinator. In this paper we provide the asymptotic behaviors and sharp upper bounds of p(t, x) and its space and time fractional derivatives $$D^n_x(-{\Delta}_x)^{\gamma}D^{\sigma}_tI^{\delta}_tp(t,x),\;{\forall}n{\in}{\mathbb{Z}}_+,\;{\gamma}{\in}[0,{\beta}],\;{\sigma},{\delta}{\in}[0,{\infty})$$, where $D^n_x$ x is a partial derivative of order n with respect to x, $(-{\Delta}_x)^{\gamma}$ is a fractional Laplace operator and $D^{\sigma}_t$ and $I^{\delta}_t$ are Riemann-Liouville fractional derivative and integral respectively.

• Communications for Statistical Applications and Methods
• /
• v.5 no.2
• /
• pp.353-359
• /
• 1998

Factorial designs with two-level factors represent the smallest factorial experiments. The system of notation and confounding and fractional factorial schemes developed for the $2^N$system are found in standard textbooks of experimental designs. Just as in the $2^N$ system, the general confounding and fractional factorial schemes are possible in $3^N,5^N$, .... , and $\rho^N$ where $\rho$ is a prime number. Hence, we have the $\rho^N$ system. In this article, the author proposes a new algorithm for constructing fractional factorial plans in the $\rho^N$ system.

• Bulletin of the Korean Mathematical Society
• /
• v.60 no.6
• /
• pp.1439-1451
• /
• 2023

This paper provides a constructive proof of the weak factorizations of the classical Hardy space H¹(ℝⁿ) in terms of multilinear fractional integral operator on the variable Lebesgue spaces, which the result is new even in the linear case. As a direct application, we obtain a new proof of the characterization of BMO(ℝⁿ) via the boundedness of commutators of the multilinear fractional integral operator on the variable Lebesgue spaces.

• Journal of applied mathematics & informatics
• /
• v.24 no.1_2
• /
• pp.167-178
• /
• 2007

This paper deals with the solutions of linear inhomogeneous time-fractional partial differential equations in applied mathematics and fluid mechanics. The fractional derivatives are described in the Caputo sense. The fractional Green function method is used to obtain solutions for time-fractional wave equation, linearized time-fractional Burgers equation, and linear time-fractional KdV equation. The new approach introduces a promising tool for solving fractional partial differential equations.

• Communications of the Korean Mathematical Society
• /
• v.31 no.4
• /
• pp.791-809
• /
• 2016

By introducing two fractional convolutions, we obtain the convolution theorems for fractional Fourier cosine and sine transforms. Applying these convolutions, we construct two Boehmian spaces and then we extend the fractional Fourier cosine and sine transforms from these Boehmian spaces into another Boehmian space with desired properties.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.7 s.337
• /
• pp.35-40
• /
• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Journal of the Korean Mathematical Society
• /
• v.57 no.6
• /
• pp.1347-1372
• /
• 2020

We study bifurcation for the following fractional Schrödinger equation $$\{\left.\begin{eqnarray}(-{\Delta})^su+V(x)u&=&{\lambda}f(u)&&{\text{in}}\;{\Omega}\\u&>&0&&{\text{in}}\;{\Omega}\\u&=&0&&{\hspace{32}}{\text{in}}\;{\mathbb{R}}^n{\backslash}{\Omega}\end{eqnarray}\right$$ where 0 < s < 1, n > 2s, Ω is a bounded smooth domain of ℝⁿ, (-∆)^s is the fractional Laplacian of order s, V is the potential energy satisfying suitable assumptions and λ is a positive real parameter. The nonlinear term f is a positive nondecreasing convex function, asymptotically linear that is $\lim_{t{\rightarrow}+{\infty}}\;{\frac{f(t)}{t}}=a{\in}(0,+{\infty})$. We discuss the existence, uniqueness and stability of a positive solution and we also prove the existence of critical value and the uniqueness of extremal solutions. We take into account the types of Bifurcation problem for a class of quasilinear fractional Schrödinger equations, we also establish the asymptotic behavior of the solution around the bifurcation point.