• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.4
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• pp.251-259
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• 2008

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other mathematical functions. Using the Taylor series and Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB and confirmed the performance of the processor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.24-29
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• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.96-105
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• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.187-193
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• 2020

Floating point arithmetic in microprocessor is the computation of addition, subtraction, multiplication, and division of floating point data to improve accuracy. In general, when designing a processor, floating point instructions are often excluded because of its complexity and only integer instructions are provided. However, in order to carry out the computations for not only engineering and technical operations but also artificial intelligence and neural networks that are in the spotlight today, floating point operations must be included. In this paper, we design a 32-bit ARMv4 family of processors with floating-point arithmetic instructions using VHDL and verify with ModelSim. As a result, ARM's floating point instructions are successfully executed.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.74-76
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• 2007

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other nonlinear functions. Using the Taylor series and the Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.659-662
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• 1999

In this paper we implement MP3 encoder based on integer operations. To implement MP3 encoder presented in ［1］, floating-point operations are required. But we devise an MP3 encoding method which is based on integer operations. To verify the method presented in this paper, we implement MP3 encoder using ARM processor. In this paper we present the method to change floating point operations into integer operations, and the ARM assembly programming technique to implement fast MP3 encoder. The MP3 encoder implement using integer processor consumes less power than the encoder implemented using floating-point processor. So the encoder implemented in this paper is suitable lot portable applications which requires low power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.234-239
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• 2006

In the past decade, several tools have been developed to automate the floating-point to fixed-point conversion for DSP systems. In the conversion process, a number of scaling shifts are introduced, and they inevitably alter the original code sequence. Recently, we have observed that a compiler can often be adversely affected by this alteration, and consequently fails to generate efficient machine code for its target processor. In this paper, we present an optimization technique that safely migrates scaling shifts to other places within the code so that the compiler can produce better-quality code. We consider our technique to be safe in that it does not introduce new overflows, yet preserving the original SQNR. The experiments on a commercial fixed-point DSP processor exhibit that our technique is effective enough to achieve tangible improvement on code size and speed for a set of benchmarks.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.98-100
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• 2005

DSPs used at motor control are usually fixed point processor. They need scaling because they cannot excute floating point calculation. Scaling for floating point calculation makes the DSP's speed down, complex coding and etc. Therefore the IQ math is adopted. IQ math makes the fixed point processor possible to calculate the floating point math. In addition, IQ math can reduce memory usage and be more faster than that without IQ math. It seems that IQ math is appropriate in motor position control. In comparison of the position calculation between the IQ math, math function and the sine table, the method using IQ math is superior than other methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.232-235
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• 1999

In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.