• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.302-309
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• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.

• Journal of Korea Multimedia Society
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• v.13 no.3
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• pp.417-429
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• 2010

Though background subtraction has been widely studied for last decades, it is still a poorly solved problem especially when it meets real environments. In this paper, we first address some common problems for background subtraction that occur in real environments and then those problems are resolved by improving an existing GMM-based background modeling method. First, to achieve low computations, fixed point operations are used. Because background model usually does not require high precision of variables, we can reduce the computation time while maintaining its accuracy by adopting fixed point operations rather than floating point operations. Secondly, to avoid erroneous backgrounds that are induced by high pedestrian traffic, static levels of pixels are examined using shot-time statistics of pixel history. By using a lower learning rate for non-static pixels, we can preserve valid backgrounds even for busy scenes where foregrounds dominate. Finally, to adapt rapid illumination changes, we estimated the intensity change between two consecutive frames as a linear transform and compensated learned background models according to the estimated transform. By applying the fixed point operation to existing GMM-based method, it was able to reduce the computation time to about 30% of the original processing time. Also, experiments on a real video with high pedestrian traffic showed that our proposed method improves the previous background modeling methods by 20% in detection rate and 5~10% in false alarm rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.1
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• pp.79-87
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• 2015

This paper proposes a floating-type wave energy conversion system that consists of a mechanical part (yo-yo vibrating system, motion rectifying system, and power transmission system) and electrical part (power generation system). The yo-yo vibrating system, which converts translational input to rotational motion, is modeled as a single degree-of-freedom system. It can amplify the wave input via the resonance phenomenon and enhance the energy conversion efficiency. The electromechanical model is established from impedance matching of the mechanical part to the electrical system. The performance was analyzed at various wave frequencies and damping ratios for a wave input acceleration of 0.14 g. The maximum output occurred at the resonance frequency and optimal load resistance, where the power conversion efficiency and electrical output power reached 48% and 290 W, respectively. Utilizing the resonance phenomenon was found to greatly enhance the performance of the wave energy converter, and there exists a maximum power point at the optimum load resistance.

• Journal of the Korean Society for Marine Environment & Energy
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• v.18 no.1
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• pp.22-28
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• 2015

The design on a riser in 1MW OTEC system is performed. The minimum diameter of the riser is decided depending on intake quantity of deep-sea water to supply an OTEC cycle. An applicable pipe material is selected from analyzing the properties of commercial pipes. The selected HDPE pipe with the low density and strength is reinforced with a lumped block attached at the end of and wire ropes along the riser. A lumped block, connected to a floating structure by wire ropes, with 25% and 50% weight of a GFRP riser is designed to be attached the end of a riser. The structural safety of the HDPE riser with wire rope supporting axial loads induced by a lumped block is analyzed under the harsh ocean environmental condition near Hawaii ocean with the numerical method. The final dimension of the riser and accessories is determined considering the economic point of view. The designed riser will be applicable to the construction of the 1 MW OTEC pilot plant.

• KSBB Journal
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• v.10 no.1
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• pp.1-8
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• 1995

A lot of water soluble proteins and lipids are released from minced mackerel meat and lost into the washing waste during the leaching process of Kamaboko or surimi manufacture. The removed proteins and lipids are not only an edible things but also a big burden for treating the wastewater. In order to recover the proteins from the effluent and to use as food stuff, the "pH-shifting" treatment, a modified isoelectric point precipitation method, was tried. This method is based on a myogen-aggregation phenomenon, which occurs when a solution of sarcoplasmic proteins is acidified or alkalified beyond the critical pH zone of 2∼3 or 12∼13 respectively and then neutralized. The maximum amount of precipitation was obtained by shifting the pH of the wastewater from original pH to isoelectric point (pH 4) or alkali pH 12 and then changing to neutral pH. The precipitates were easily collected by filteration or centrifuging at 10,000rpm. The oils which were only floating in the washing wastewater are easily recovered by seperating with oil separator after pouring. The recovered proteins were slightly denaturated during this pH shifting precipitation process, while the composition of amino acids was good balance as a food.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.535-542
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• 1995

In this paper we present two preconditioners for solving large sparse linear systems arising from elliptic partial differential equations on massively parallel machines, such as the CM-5. Most massively parallel machines do heavily rely on the message-passing for the interprocessor communications. but according to the current manufacturing standards the cost of communications is very high compared to that of floating point arithmetic computations. Due to this we need an algorithm which minimizes the amount of interprocessor communication on the massively parallel machines. We will show that Block SOR(Successive Over Relaxation) method coupled with the multi-coloring technique is one of such preconditioner on the massively parallel machines, by conducting experiments in the CM-5. Also, we implemented the ADI(Alternation Direction Implicit) method in the CM-5, which has been conventionally one of the most powerful parallel preconditioner. Our experiment shows that Block SOR method coupled with the multi-coloring technique could yield a speedup with 50% efficiency with the range of number of processors form 16 to 512 for a matrix with dimension 512x512. On the other hand, the ADI method shows a very poor performance.

• Korean Institute of Interior Design Journal
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• v.23 no.6
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• pp.51-59
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• 2014

Rem Koolhaas has pursued new architectural approaches breaking with conventional ones. Around the 1990s when large-scale projects occurred with the union of Europe ahead, Koolhaas recognized the limits to the existing methods for responding to such changes. Accordingly, he came to use design methods based on 'congestion' and 'void' as strategical alternatives, which became the moment for him to leap forward from the previous working sphere based in Europe to becoming an architect who would be commissioned a number of large-scale global projects. Therefore, this study intends to investigate his design methods which utilized congestion and void, and to derive spatial characteristics from the projects based on such methods. First of all, the study looked into the historical background, definition and process of congestion and the void as design methods, and analyzed his projects to which such methods were applied by classifying them into the following categories: 1) the void that removes a space of singularity; 2) the void that penetrates space while making a flow; and 3) the void that is formed by vertical extrusion. Then, the characteristics of architectural spaces made in this way were identified as 1)the single-body appearance made by congestion and the following types of space made by the void: 2) the non-uniformly shaped space that looks like floating; 3) the flexible space with various flows and directions; and 4) the space with virtual possibilities that embrace contingent events. This understanding of Rem Koolhaas's design methods which were attempted in various ways at his critical turning point will be the foundation to understand the overall world of his works.

• Journal of Power System Engineering
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• v.17 no.3
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• pp.89-98
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• 2013

In this paper, the authors consider control system design problem of barge type surface vessel. It is based on the Dynamic Positioning System(DPS) design problem. The main role of barge ship is to carry and supply the materials to the floating units and other places. To carry out this job, it should be positioned in the specified area. Even though sometimes the thrust systems are installed on it, in general the mooring winch system with the rope is used. It may be difficult to compare the control performances of two types. But, if we consider this problem in point of usefulness, we can easily find out that the winch control system is more useful and applicable to the real field than the thrust control system except a special use. Therefore, in this paper we consider a single type mooring winch system and control system design problem in which accurate position control is needed. Because this result can be extended to the general type mooring system in which a number of winch are installed. At first, a mathematical model of winch is obtained and evaluated to verify the usefulness for control system design by experiment. Also, the disturbance model is extracted from experiment data to evaluate the strength of the uncertainty. Based on this results, the robust control system is designed and control performance is evaluated by simulation.

• The Journal of the Acoustical Society of Korea
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• v.14 no.1E
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• pp.83-87
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• 1995

The implementation of the voice dodec is imjplemented by using TMS320C30, which is the floating point DSP chip from Texas Instrument. QCELP (Qualcomm Code Excited Linear Prediction) is used to encode and decode the voice. The QCELP code is implemented by the TMS320C30 C-dode. The DSP board is controlled by the PC. The PC program tranfors the voice file from and to the DSP board, which is also implemented by C-code. The voice is encoded by the DSP board and the encoded data is transferred to PC to be stored as a file. To hear the voice. the voice data file is sent to DSP board and decoded to synthesize audible voice. Two flags are used by both programs to notify the status of the operation. By checking the flags, DSP and PC decides when the voice data is transferred between them.