• KSCE Journal of Civil and Environmental Engineering Research
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• v.33 no.1
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• pp.13-22
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• 2013

This paper deals with a novel method for numerical analyses of the tapered geometrical non-linear beam with three unknown parameters, subjected a floating point load. The beams with hinged-movable end constraint are chosen as the objective beam. Cross sections of the beam whose flexural rigidities are functionally varied with the axial coordinate. The first order simultaneous differential equations governing the elastica of such beam are derived on the basis of the Bernoulli-Euler beam theory. A novel numerical method for solving these equations is developed by using the iteration technique. The processes of the solution method are extensively discussed through a typical numerical example. For validating theories developed herein, laboratory scaled experiments are conducted.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.55-65
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• 1995

Existing multiple-row downdating algorithms have adopted a CFD(Cholesky Factor Downdating) that recursively downdates one row at a time. The CFD based algorithm requires 5/2p $n^{2}$ flops(floating point operations) downdating a p$\times$n observation matrix $Z^{T}$ . On the other hands, a HCFD(Hybrid CFD) based algorithm we propose in this paper, requires p $n^{2}$＋6/5 $n^{3}$ flops v hen p$\geq$n. Such a HCFD based algorithm factorizes $Z^{T}$ at first, such that $Z^{T}$ = $Q_{z}$ RT/Z, and then applies the CFD onto the upper triangular matrix Rt/z, so that the total number of floating point operations for downdating $Z^{T}$ would be significantly reduced compared with that of the CFD based algorithm. Benchmark tests on the Sun SPARC/2 and the Tolerant System also show that performance of the HCFD based algorithm is superior to that of the CFD based algorithm, especially when the number of rows of the observation matrix is large.rge.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1183-1188
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• 2005

In this paper, we propose a 3D automated measuring system which measures the mandibular movements and the reference plane of the jaw movements. In diagnosis and treatment of the malocclusions, it is necessary to estimate the mandibular movements and the reference plane of the jaw movements. The proposed system is configured with double stereo-cameras, PC, two moving pattern plates(MPPs), two fixed pattern plates(FPPs) and one orbital marker. The virtual pattern plate is applied to calculate the homogeneous transformation matrices which describe the coordinates systems of the FPP and MPP with respect to the world coordinates system. To estimate the parameters of the hinge axis, the Euler's theorem is applied. The hinge axis points are intersections between the FPPs and the hinge axis. The coordinates of a hinge axis point with respect to the MPP coordinates system are set up to fixed value. And then, the paths of the jaw movement can be calculated by applying the homogeneous transformation matrix to fixed hinge axis point. To examine the accuracy of the measurements, experiments of measuring the hinge axis points and floating paths of them are performed using the jaw motion simulator. As results, the measurement errors of the hinge axis points are within reasonable boundary, and the floating paths are very similar to the simulator's moving path.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.12
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• pp.1079-1085
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• 2012

For precise motion control, S-curve velocity profile is generally used but it has disadvantage of relatively long calculation time for floating-point arithmetics. In this paper, we present a new generating method for velocity profile to reduce delay time of profile generation so that it overcomes such disadvantage and enhances the efficiency of precise motion control. In this approach, the velocity profile is designed based on the gamma correction expression that is generally used in image processing to obtain a smoother movement without any critical jerk. The proposed velocity profile is designed to support both T-curve and S-curve velocity profile. It can generate precise profile by adding an offset to the velocity profile with decimals under floating point that are not counted during gamma correction arithmetic operation. As a result, the operation time is saved and the efficiency is improved. The proposed method is compared with the existing method that generates velocity profile using ring buffer on a 8-bit low-cost MCU. The result shows that the proposed method has no delay in generating driving profile with good accuracy of each cycle velocity. The significance of the proposed method lies in reduction of the operation time without degrading the motion accuracy. Generated driving signal also shows to verify effectiveness of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.31-38
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• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.37-44
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• 2000

In this paper, we described the real-time implementation effort of MPEG-4 audio HVXC (Harmonic Vector eXcitation Coding) algorithm for very low bitrates, which has target applications from mobile communications to Internet telephony, on current high performance floating point TMS320C6701 DSP. We adopted a hardware structure for real-time operation. In order for software optimization, we used C- and assembly-language level optimizations for time-critical functional codes. Utilizing the internal program memory of the DSP as the program cache, the internal data memory overlap technique and DMA functionality, we could get a goal of realtime operation of HVXC codec both at 2 kbit/s and at 4 kbit/s. For an encoder at 2 kbit/s, the optimization ratio to original code is about 96 %. Finally, we got the subjective quality of MOS 2.45 at 2 kbit/s from an informal quality test.

• Journal of the Korean Magnetics Society
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• v.15 no.2
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• pp.113-117
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• 2005

Multiferroic $HoMnO_3$ single crystal was prepared using 4-point focused floating zone furnace, and polycrystalline $HoMn_{1-x}\;^57Fe_xO_3$ (x=0.00, 0.01, 0.02, 0.05) powders have been prepared by solid state reaction. Their magnetic and crystallographic properties are studied using MPMS, PPMS, and $M\ddot{o}ssbauer$ spectroscopy. The crystal structure found to be a hexagonal and a magnetic easy-axis is (110) direction. As the external applied magnetic field increases, temperature of the dielectric constant anomaly is decreased. $HoMn_{0.95}\;^{57}Fe_{0.05}O_3$ shows huge quadrupole splitting value from the $M\ddot{o}ssbauer$ spectra.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.57-67
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• 2006

Intellectual property rights are gathering strength theses days. Because digital contents are easily reproduced and distributed by advanced computers and networks. Digital watermarking is one of the best solutions for this problem. Generally, frequency-domain watermarking algorithms are preferred since they are more robust than spatial-domain algorithms. However, coefficients in the frequency domain are floating-point numbers. Thus, it is not easy to manipulate those floating-point coefficients and frequency-domain watermarking algorithms have some limitations in their applications. In order to overcome this difficulty, we employ an integer transform in this paper. In addition, our proposed algerian can extract the watermark from both the spatial and frequency domains. We embed the watermark into a specific bit-plane of mid-frequency coefficients. This is equivalent to the differential energy watermarking (DEW) in the spatial domain. Our simulation results show that the proposed algorithm is imperceptible, good for the watermark payload, and robustness against various attacks. Moreover, it is more efficient than any other algorithm working in only one domain.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.49-54
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• 2007

As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.