• Title/Summary/Keyword: floating metal

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Effect of MIM and n-Well Capacitors on Programming Characteristics of EEPROM

  • Lee, Chan-Soo;Cui, Zhi-Yuan;Jin, Hai-Feng;Sung, Si-Woo;Lee, Hyung-Gyoo;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.1
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    • pp.35-39
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    • 2011
  • An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

A Study on the Distribution and Composition of Floating Debris in the Coast of Korea I. Southeastern Sea (연안어장의 부유성 폐기물 분포와 조성에 관한 연구 I . 남해 동부해역)

  • 김종화
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.34 no.3
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    • pp.287-293
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    • 1998
  • Floating debris was recorded from a training ship, #1 Kwarnksan, of Pukyong National University with about 10 knots speed during March, May and July of 1997. The area sampled is the Southeastern Coast of Korea, divided into 40 unit segments on survey routes. Debris fabrication materials were categorized using the following ; man-made or natural wood items, paper, cardboard, nylon rope, netting, styrofoam and plastics, floating metal and glass containers. All identified items within a $100\;{\pm}\;2\;m$ wide band were recorded but ignored if beyond this boundary.The results of distribution and composition of floating debris in the area as follows:1. The quantities of debris during the duration of survey were distributed from 2~605 items per km2. The most obvious trend is the widespread distribution of all debris. 2. The highest densities of all debris were discovered in the coastal waters of Seoimal lighthouse, the southeastern part of Koje island, next near Nakdong estuaries. Especially styrofoam & plastics were observed in 77.4~87.2% of sampled area, next is wood items, 9.1~ 13.5%. And nylon netting & rope, 3.6%, was the third item of pollutant. Others are very small. 3. Compared with the East Coat of Korea, the quantities of all debus in theSoutheastern Sea are 6 times as large as the East Coast. The survey provides a basis for more detailed survey work in the South Sea. Further surveys are being investigated, and from this it is hoped that a much wider coverage can be achieved, perhaps on all sites of the Coast of Korea and contributed to the removal method, finding of sources, stationary area of debris.

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Distribution and Composition of Floating Debris in the East Coast of Korea (한국 동해 연안어장의 부유성 폐기물 분포와 조성)

  • Kim, Jong-Hwa;Kim, Sam-Kon;Park, Chang-Doo;Ju, Su-Dong
    • Journal of Fisheries and Marine Sciences Education
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    • v.9 no.1
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    • pp.31-39
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    • 1997
  • Floating debris was recorded from a training ship, #1 Kwanaksan, of Pukyong National University with about 10 knots speed during August 19~26, 1996. The area sampled is the East Coast of Korea, divided into 33 unit segments on survey routes. Debris fabrication materials were categorized using the following; man-made or natural wood items, paper, cardboard, nylon rope, netting, styrofoam and plastics, floating metal and glass containers. All identified items within a $100{\pm}2m$ wide band were recorded but ignored if beyond this boundary. The results of distribution and composition of floating debris in the area are as follows: 1. The quantities of debris during the summer were distributed from 1.8~52 items per $km^2$. The most obvious trend is the widespread distribution of all debris. 2. The highest densities of all debris were discovered in the vicinity of Pusan and ills an area. Especially styrofoam & plastics were observed in 81% of sampled area, next is wood items, 9.1%. Nylon netting & rope was the least widespread pollutant. 3. The relationship between distribution of debris and surface currents of the area was not apparently revealed through this survey. Further surveys are being instigated, and from this it is hoped that a much wider coverage can be achived, perhaps on all sites of Southern and Western sea of Korea and contributed to the finding of sources,stationary area of debris.

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[Li]/[Nb]조성비 변화에 따른 iron-doped $LiNbO_3$ 결정의 특성분석

  • 한지웅;원종원;오근호
    • Proceedings of the Korea Association of Crystal Growth Conference
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    • 1997.10a
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    • pp.111-115
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    • 1997
  • Iron-doped LiNbO$_3$ crystals were grown by floating zone(FZ) method with different [Li]/[Nb] ratio in order to investigate doping effects of transition metal impurity in LiNbO$_3$ crystal. The grown crystals were analyized edge in UV/VIS/IR spectrometry and EPMA(electron probe micro-analysis). The absorption edge in UV-VIS region and OH-absorption peak in IR region were investigated. The change of Fe concentration along the solidification direction was also investigated

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CMOS Binary Image Sensor Using Double-Tail Comparator with High-Speed and Low-Power Consumption

  • Kwen, Hyeunwoo;Jang, Junyoung;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.30 no.2
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    • pp.82-87
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    • 2021
  • In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

A Study on the Characteristics and Programming Conditions of the Scaled SONOSFET NVSM for Flash Memory (플래시메모리를 위한 Scaled SONOSFET NVSM의 프로그래밍 조건과 특성에 관한 연구)

  • 박희정;박승진;남동우;김병철;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.11
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    • pp.914-920
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    • 2000
  • When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

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Nonvolatile Memory and Photovoltaic Devices Using Nanoparticles

  • Kim, Eun Kyu;Lee, Dong Uk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.79-79
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    • 2013
  • Quantum-structures with nanoparticles have been attractive for various electronic and photonic devices [1,2]. In recent, nonvolatile memories such as nano-floating gate memory (NFGM) and resistance random access memory (ReRAM) have been studied using silicides, metals, and metal oxides nanoparticles [3,4]. In this study, we fabricated nonvolatile memories with silicides (WSi2, Ti2Si, V2Si) and metal-oxide (Cu2O, Fe2O3, ZnO, SnO2, In2O3 and etc.) nanoparticles embedded in polyimide matrix, and photovoltaic device also with SiC nanoparticles. The capacitance-voltageand current-voltage data showed a threshold voltage shift as a function of write/erase voltage, which implies the carrier charging and discharging into the metal-oxide nanoparticles. We have investigated also the electrical properties of ReRAM consisted with the nanoparticles embedded in ZnO, SiO2, polyimide layer on the monolayered graphene. We will discuss what the current bistability of the nanoparticle ReRAM with monolayered graphene, which occurred as a result of fully functional operation of the nonvolatile memory device. A photovoltaic device structure with nanoparticles was fabricated and its optical properties were also studied by photoluminescence and UV-Vis absorption measurements. We will discuss a feasibility of nanoparticles to application of nonvolatile memories and photovoltaic devices.

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The Production of Metal Matrix Composites by Using the EPC Process;Particle Behavior at Solid-Liquid Interface (소실모형주조법에 의한 금속기 복합재료의 제조;고액계면과 입자거동에 관하여)

  • Park, Jong-Ik;Kim, Young-Seob;Kim, Jeong-Min;Kim, Dong-Gyu
    • Journal of Korea Foundry Society
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    • v.17 no.1
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    • pp.93-99
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    • 1997
  • A possibility of production of aluminium matrix composites by using the lost foam process was investigated. Silicon carbide particles, graphite particles, and stainless steel wires were used as reinforcement materials. The reinforcement materials were introduced to the polystyrene to form patterns via injection molding process. The results obtained from this experiment can be summarized as follows. In Al/SiCp system, the particles with the radius of $100{\mu}m$ and over were entrapped in the matrix in the case of upward freezing of which solidification direction was opposite to floating direction of the particles. And few particles were entrapped in the matrix in downward freezing. In Al/graphite system, almost no particles were entrapped in the matrix except the area chill attatched. When the thickness of polystyrene slice was 4mm in Al/stainless steel wire system, the floating tendency of fibers was observed to increase as the distance from the ingate was increased.

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A study on characteristics of the scaled SONOSFET NVSM for Flash memory (플래시메모리를 위한 scaled SONOSFET NVSM 의 프로그래밍 조건과 특성에 관한 연구)

  • 박희정;박승진;홍순혁;남동우;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.751-754
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    • 2000
  • When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

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Simulation Study on Silicon-Based Floating Body Synaptic Transistor with Short- and Long-Term Memory Functions and Its Spike Timing-Dependent Plasticity

  • Kim, Hyungjin;Cho, Seongjae;Sun, Min-Chul;Park, Jungjin;Hwang, Sungmin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.657-663
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    • 2016
  • In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.